7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter, decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared).
7
1
WDGA
`rw`
Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA=1, the watchdog can generate a reset.
Rejestr: CFR0x40002C04
rw
Configuration register
Bit
Szer.
Pole
Dostęp
Opis
0–6
7
W
`rw`
7-bit window value These bits contain the window value to be compared with the down-counter.
9
1
EWI
`rw`
Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset.
11–13
3
WDGTB:
—
Timer base The timebase of the prescaler can be modified as follows: