Timery

TIM15 0x40014000

21 rejestrów/klastrów w tym peryferium.

Rejestr: CR1 0x40014000

control register 1

Bit	Szer.	Pole	Dostęp	Opis
0	1	CEN	`rw`	Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
1	1	UDIS	`rw`	Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
2	1	URS	`rw`	Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
3	1	OPM	`rw`	One-pulse mode
7	1	ARPE	`rw`	Auto-reload preload enable
8–9	2	CKD	`rw`	Clock division This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters (TIx)
11	1	UIFREMAP	`rw`	UIF status bit remapping

Rejestr: CR2 0x40014004

control register 2

Bit	Szer.	Pole	Dostęp	Opis
0	1	CCPC	`rw`	Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
2	1	CCUS	`rw`	Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
3	1	CCDS	`rw`	Capture/compare DMA selection
4–6	3	MMS	`rw`	Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:
7	1	TI1S	`rw`	TI1 selection
8	1	OIS1	`rw`	Output Idle state (OC1 output)
9	1	OIS1N	`rw`	Output Idle state (OC1N output)
10	1	OIS2	`rw`	Output Idle state (OC2 output)

Rejestr: SMCR 0x40014008

slave mode control register

Bit	Szer.	Pole	Dostęp	Opis
0–2	3	SMS	`rw`	Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS='00100'). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
4–6	3	TS	`rw`	Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
7	1	MSM	`rw`	Master/slave mode
16	1	SMS_3	`rw`	Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS='00100'). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
20–21	2	TS2	`rw`	Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.

Rejestr: DIER 0x4001400C

DMA/Interrupt enable register

Bit	Szer.	Pole	Dostęp	Opis
0	1	UIE	`rw`	Update interrupt enable
1	1	CC1IE	`rw`	Capture/Compare 1 interrupt enable
2	1	CC2IE	`rw`	Capture/Compare 2 interrupt enable
5	1	COMIE	`rw`	COM interrupt enable
6	1	TIE	`rw`	Trigger interrupt enable
7	1	BIE	`rw`	Break interrupt enable
8	1	UDE	`rw`	Update DMA request enable
9	1	CC1DE	`rw`	Capture/Compare 1 DMA request enable
10	1	CC2DE	`rw`	Capture/Compare 2 DMA request enable
13	1	COMDE	`rw`	COM DMA request enable
14	1	TDE	`rw`	Trigger DMA request enable

Rejestr: SR 0x40014010

status register

Bit	Szer.	Pole	Dostęp	Opis
0	1	UIF	`rw`	Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
1	1	CC1IF	`rw`	Capture/compare 1 interrupt flag
2	1	CC2IF	`rw`	Capture/compare 2 interrupt flag
5	1	COMIF	`rw`	COM interrupt flag
6	1	TIF	`rw`	Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
7	1	BIF	`rw`	Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
9	1	CC1OF	`rw`	Capture/Compare 1 overcapture flag
10	1	CC2OF	`rw`	Capture/Compare 2 overcapture flag

Rejestr: EGR 0x40014014

event generation register

Bit	Szer.	Pole	Dostęp	Opis
0	1	UG	`wo`	Update generation This bit can be set by software, it is automatically cleared by hardware.
1	1	CC1G	`wo`	Capture/compare 1 generation
2	1	CC2G	`wo`	Capture/compare 2 generation
5	1	COMG	`rw`	Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output.
6	1	TG	`wo`	Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
7	1	BG	`wo`	Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.

Rejestr: CCMR1_Input 0x40014018

capture/compare mode register 1 (input mode)

Brak zdefiniowanych pól bitowych.

Rejestr: CCMR1_Output 0x40014018

capture/compare mode register (output mode)

Bit	Szer.	Pole	Dostęp	Opis
0–1	2	CC1S	`rw`	Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER).
0–1	2	CC1S	`rw`	Capture/Compare 1 selection
2	1	OC1FE	`rw`	Output compare 1 fast enable
2–3	2	IC1PSC	`rw`	Input capture 1 prescaler
3	1	OC1PE	`rw`	Output compare 1 preload enable
4–6	3	OC1M	`rw`	Output compare 1 mode
4–7	4	IC1F	`rw`	Input capture 1 filter
8–9	2	CC2S	`rw`	Capture/Compare 2 selection
8–9	2	CC2S	`rw`	Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER).
10	1	OC2FE	`rw`	Output compare 2 fast enable
10–11	2	IC2PSC	`rw`	Input capture 2 prescaler
11	1	OC2PE	`rw`	Output compare 2 preload enable
12–14	3	OC2M	`rw`	Output compare 2 mode
12–15	4	IC2F	`rw`	Input capture 2 filter
16	1	OC1M_3	`rw`	Output compare 1 mode, bit 3
24	1	OC2M_3	`rw`	Output compare 2 mode, bit 3

Rejestr: CCER 0x40014020

capture/compare enable register

Bit	Szer.	Pole	Dostęp	Opis
0	1	CC1E	`rw`	Capture/Compare 1 output enable
1	1	CC1P	`rw`	Capture/Compare 1 output Polarity
2	1	CC1NE	`rw`	Capture/Compare 1 complementary output enable
3	1	CC1NP	`rw`	Capture/Compare 1 output Polarity
4	1	CC2E	`rw`	Capture/Compare 2 output enable
5	1	CC2P	`rw`	Capture/Compare 2 output Polarity
7	1	CC2NP	`rw`	Capture/Compare 2 output Polarity

Rejestr: CNT16 0x40014024

16-bit counter register

Brak zdefiniowanych pól bitowych.

Rejestr: CNT: 0x40014024

counter

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	CNT	`rw`	counter value
0–15	16	CNT	`rw`	counter value
31	1	UIFCPY	`ro`	UIF Copy

Rejestr: PSC 0x40014028

prescaler

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	PSC:	—	Prescaler value

Rejestr: ARR 0x4001402C

auto-reload register

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	ARR:	—	Auto-reload value

Rejestr: RCR 0x40014030

repetition counter register

Bit	Szer.	Pole	Dostęp	Opis
0–7	8	REP:	—	Repetition counter value

Rejestr: CCR1 0x40014034

capture/compare register

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	CCR:	—	Capture/Compare value

Rejestr: CCR2 0x40014038

capture/compare register

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	CCR:	—	Capture/Compare value

Rejestr: BDTR 0x40014044

break and dead-time register

Bit	Szer.	Pole	Dostęp	Opis
0–7	8	DTG	`rw`	Dead-time generator setup
8–9	2	LOCK	`rw`	Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
10	1	OSSI	`rw`	Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
11	1	OSSR	`rw`	Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
12	1	BKE	`rw`	Break enable 1; Break inputs (BRK and CCS clock failure event) enabled This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
13	1	BKP	`rw`	Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
14	1	AOE	`rw`	Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
15	1	MOE	`rw`	Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page818).
16–19	4	BKF	`rw`	Break filter This bit-field defines the frequency used to sample the BRK input signal and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
26	1	BKDSRM	`rw`	Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
28	1	BKBID	`rw`	Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

Rejestr: DCR 0x40014048

DMA control register

Bit	Szer.	Pole	Dostęp	Opis
0–4	5	DBA	`rw`	DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ...
8–12	5	DBL	`rw`	DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ...

Rejestr: DMAR 0x4001404C

DMA address for full transfer

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	DMAB:	—	DMA register for burst accesses

Rejestr: AF1 0x40014060

TIM15 alternate register 1

Bit	Szer.	Pole	Dostęp	Opis
0	1	BKINE	`rw`	BRK BKIN input enable This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
1	1	BKCMP1E	`rw`	BRK COMP1 enable This bit enables the COMP1 for the timer's BRK input. COMP1 output is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
2	1	BKCMP2E	`rw`	BRK COMP2 enable This bit enables the COMP2 for the timer's BRK input. COMP2 output is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
9	1	BKINP	`rw`	BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
10	1	BKCMP1P	`rw`	BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
11	1	BKCMP2P	`rw`	BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Rejestr: TISEL 0x40014068

input selection register

Bit	Szer.	Pole	Dostęp	Opis
0–3	4	TI1SEL	`rw`	selects TI1[0] to TI1[15] input Others: Reserved
8–11	4	TI2SEL	`rw`	selects TI2[0] to TI2[15] input Others: Reserved