Timery

TIM14 0x40002000

13 rejestrów/klastrów w tym peryferium.

Rejestr: CR1 0x40002000

rw

control register 1

Bit	Szer.	Pole	Dostęp	Opis
0	1	CEN	`rw`	Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
1	1	UDIS	`rw`	Update disable This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. Counter overflow Setting the UG bit. Buffered registers are then loaded with their preload values.
2	1	URS	`rw`	Update request source This bit is set and cleared by software to select the update interrupt (UEV) sources. Counter overflow Setting the UG bit
3	1	OPM	`rw`	One-pulse mode
7	1	ARPE	`rw`	Auto-reload preload enable
8–9	2	CKD	`rw`	Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx),
11	1	UIFREMAP	`rw`	UIF status bit remapping

Rejestr: DIER 0x4000200C

rw

DMA/Interrupt enable register

Bit	Szer.	Pole	Dostęp	Opis
0	1	UIE	`rw`	Update interrupt enable
1	1	CC1IE	`rw`	Capture/Compare 1 interrupt enable

Rejestr: SR 0x40002010

rw

status register

Bit	Szer.	Pole	Dostęp	Opis
0	1	UIF	`rw`	Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS='0' in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS='0' and UDIS='0' in the TIMx_CR1 register.
1	1	CC1IF	`rw`	Capture/compare 1 interrupt flag
9	1	CC1OF	`rw`	Capture/Compare 1 overcapture flag

Rejestr: EGR 0x40002014

wo

event generation register

Bit	Szer.	Pole	Dostęp	Opis
0	1	UG	`wo`	Update generation This bit can be set by software, it is automatically cleared by hardware.
1	1	CC1G	`wo`	Capture/compare 1 generation

Rejestr: CCMR1_Input 0x40002018

rw

capture/compare mode register 1 (input mode)

Brak zdefiniowanych pól bitowych.

Rejestr: CCMR1_Output 0x40002018

rw

capture/compare mode register 1 (output mode)

Bit	Szer.	Pole	Dostęp	Opis
0–1	2	CC1S	`rw`	Capture/Compare 1 selection
0–1	2	CC1S	`rw`	Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
2	1	OC1FE	`rw`	Output compare 1 fast enable
2–3	2	IC1PSC	`rw`	Input capture 1 prescaler
3	1	OC1PE	`rw`	Output compare 1 preload enable
4–6	3	OC1M	`rw`	Output compare 1 mode
4–7	4	IC1F	`rw`	Input capture 1 filter
16	1	OC1M_3	`rw`	Output compare 1 mode, bit 3

Rejestr: CCER 0x40002020

rw

capture/compare enable register

Bit	Szer.	Pole	Dostęp	Opis
0	1	CC1E	`rw`	Capture/Compare 1 output enable
1	1	CC1P	`rw`	Capture/Compare 1 output Polarity
3	1	CC1NP	`rw`	Capture/Compare 1 output Polarity

Rejestr: CNT 0x40002024

rw

counter

Brak zdefiniowanych pól bitowych.

Rejestr: CNT16 0x40002024

rw

16-bit counter register

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	CNT	`rw`	counter value
0–15	16	CNT:	—	low counter value
31	1	UIFCPY:	—	UIF Copy

Rejestr: PSC 0x40002028

rw

prescaler

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	PSC:	—	Prescaler value

Rejestr: ARR 0x4000202C

rw

auto-reload register

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	ARR:	—	Low Auto-reload value

Rejestr: CCR1 0x40002034

rw

capture/compare register

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	CCR:	—	Capture/Compare value

Rejestr: TISEL 0x40002068

rw

TIM timer input selection register

Bit	Szer.	Pole	Dostęp	Opis
0–3	4	TI1SEL	`rw`	selects TI1[0] to TI1[15] input Others: Reserved