Timery

TIM1 0x40012C00

30 rejestrów/klastrów w tym peryferium.

Rejestr: CR1 0x40012C00

control register 1

Bit	Szer.	Pole	Dostęp	Opis
0	1	CEN	`rw`	Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
1	1	UDIS	`rw`	Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
2	1	URS	`rw`	Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
3	1	OPM	`rw`	One pulse mode
4	1	DIR	`rw`	Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.
5–6	2	CMS	`rw`	Center-aligned mode selection Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed
7	1	ARPE	`rw`	Auto-reload preload enable
8–9	2	CKD	`rw`	Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (ETR, TIx): Note: tDTS = 1/fDTS, tCK_INT = 1/fCK_INT.
11	1	UIFREMAP	`rw`	UIF status bit remapping

Rejestr: CR2 0x40012C04

control register 2

Bit	Szer.	Pole	Dostęp	Opis
0	1	CCPC	`rw`	Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
2	1	CCUS	`rw`	Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
3	1	CCDS	`rw`	Capture/compare DMA selection
4–6	3	MMS	`rw`	Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
7	1	TI1S	`rw`	TI1 selection
8	1	OIS1	`rw`	Output Idle state (OC1 output)
9	1	OIS1N	`rw`	Output Idle state (OC1N output)
10	1	OIS2	`rw`	Output Idle state (OC2 output)
11	1	OIS2N	`rw`	Output Idle state (OC2N output)
12	1	OIS3	`rw`	Output Idle state (OC3 output)
13	1	OIS3N	`rw`	Output Idle state (OC3N output)
14	1	OIS4	`rw`	Output Idle state (OC4 output)
16	1	OIS5	`rw`	Output Idle state (OC5 output)
18	1	OIS6	`rw`	Output Idle state (OC6 output)
20–23	4	MMS2	`rw`	Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

Rejestr: SMCR 0x40012C08

slave mode control register

Bit	Szer.	Pole	Dostęp	Opis
0–2	3	SMS	`rw`	Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
3	1	OCCS	`rw`	OCREF clear selection This bit is used to select the OCREF clear source.
4–6	3	TS	`rw`	Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
7	1	MSM	`rw`	Master/slave mode
8–11	4	ETF	`rw`	External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
12–13	2	ETPS	`rw`	External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
14	1	ECE	`rw`	External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
15	1	ETP	`rw`	External trigger polarity This bit selects whether ETR or ETR is used for trigger operations
16	1	SMS_3	`rw`	Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
20–21	2	TS2	`rw`	Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.

Rejestr: DIER 0x40012C0C

DMA/Interrupt enable register

Bit	Szer.	Pole	Dostęp	Opis
0	1	UIE	`rw`	Update interrupt enable
1	1	CC1IE	`rw`	Capture/Compare 1 interrupt enable
2	1	CC2IE	`rw`	Capture/Compare 2 interrupt enable
3	1	CC3IE	`rw`	Capture/Compare 3 interrupt enable
4	1	CC4IE	`rw`	Capture/Compare 4 interrupt enable
5	1	COMIE	`rw`	COM interrupt enable
6	1	TIE	`rw`	Trigger interrupt enable
7	1	BIE	`rw`	Break interrupt enable
8	1	UDE	`rw`	Update DMA request enable
9	1	CC1DE	`rw`	Capture/Compare 1 DMA request enable
10	1	CC2DE	`rw`	Capture/Compare 2 DMA request enable
11	1	CC3DE	`rw`	Capture/Compare 3 DMA request enable
12	1	CC4DE	`rw`	Capture/Compare 4 DMA request enable
13	1	COMDE	`rw`	COM DMA request enable
14	1	TDE	`rw`	Trigger DMA request enable

Rejestr: SR 0x40012C10

status register

Bit	Szer.	Pole	Dostęp	Opis
0	1	UIF	`rw`	Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM1_SMCRTIMx_SMCR)N/A), if URS=0 and UDIS=0 in the TIMx_CR1 register.
1	1	CC1IF	`rw`	Capture/compare 1 interrupt flag
2	1	CC2IF	`rw`	Capture/compare 2 interrupt flag
3	1	CC3IF	`rw`	Capture/compare 3 interrupt flag
4	1	CC4IF	`rw`	Capture/compare 4 interrupt flag
5	1	COMIF	`rw`	COM interrupt flag
6	1	TIF	`rw`	Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
7	1	BIF	`rw`	Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
8	1	B2IF	`rw`	Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active.
9	1	CC1OF	`rw`	Capture/Compare 1 overcapture flag
10	1	CC2OF	`rw`	Capture/Compare 2 overcapture flag
11	1	CC3OF	`rw`	Capture/Compare 3 overcapture flag
12	1	CC4OF	`rw`	Capture/Compare 4 overcapture flag
13	1	SBIF	`rw`	System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation.
16	1	CC5IF	`rw`	Compare 5 interrupt flag Refer to CC1IF description (Note: Channel 5 can only be configured as output)
17	1	CC6IF	`rw`	Compare 6 interrupt flag Refer to CC1IF description (Note: Channel 6 can only be configured as output)

Rejestr: EGR 0x40012C14

event generation register

Bit	Szer.	Pole	Dostęp	Opis
0	1	UG	`wo`	Update generation This bit can be set by software, it is automatically cleared by hardware.
1	1	CC1G	`wo`	Capture/compare 1 generation
2	1	CC2G	`wo`	Capture/compare 2 generation
3	1	CC3G	`wo`	Capture/compare 3 generation
4	1	CC4G	`wo`	Capture/compare 4 generation
5	1	COMG	`wo`	Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output.
6	1	TG	`wo`	Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
7	1	BG	`wo`	Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
8	1	B2G	`wo`	Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.

Rejestr: CCMR1_Input 0x40012C18

capture/compare mode register 1 (output mode)

Brak zdefiniowanych pól bitowych.

Rejestr: CCMR1_Output 0x40012C18

capture/compare mode register 1 (output mode)

Bit	Szer.	Pole	Dostęp	Opis
0–1	2	CC1S	`rw`	Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER).
0–1	2	CC1S	`rw`	Capture/Compare 1 selection
2	1	OC1FE	`rw`	Output compare 1 fast enable
2–3	2	IC1PSC	`rw`	Input capture 1 prescaler
3	1	OC1PE	`rw`	Output compare 1 preload enable
4–6	3	OC1M	`rw`	Output compare 1 mode
4–7	4	IC1F	`rw`	Input capture 1 filter
7	1	OC1CE	`rw`	Output compare 1 clear enable
8–9	2	CC2S	`rw`	Capture/Compare 2 selection
8–9	2	CC2S	`rw`	Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER).
10	1	OC2FE	`rw`	Output compare 2 fast enable
10–11	2	IC2PSC	`rw`	Input capture 2 prescaler
11	1	OC2PE	`rw`	Output compare 2 preload enable
12–14	3	OC2M	`rw`	Output compare 2 mode
12–15	4	IC2F	`rw`	Input capture 2 filter
15	1	OC2CE	`rw`	Output compare 2 clear enable
16	1	OC1M_3	`rw`	Output compare 1 mode, bit 3
24	1	OC2M_3	`rw`	Output compare 2 mode, bit 3

Rejestr: CCMR2_Input 0x40012C1C

capture/compare mode register 2 (output mode)

Brak zdefiniowanych pól bitowych.

Rejestr: CCMR2_Output 0x40012C1C

capture/compare mode register 2 (output mode)

Bit	Szer.	Pole	Dostęp	Opis
0–1	2	CC3S	`rw`	Capture/Compare 3 selection
0–1	2	CC3S	`rw`	Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER).
2	1	OC3FE	`rw`	Output compare 3 fast enable
2–3	2	IC3PSC	`rw`	Input capture 3 prescaler
3	1	OC3PE	`rw`	Output compare 3 preload enable
4–6	3	OC3M	`rw`	Output compare 3 mode
4–7	4	IC3F	`rw`	Input capture 3 filter
7	1	OC3CE	`rw`	Output compare 3 clear enable
8–9	2	CC4S	`rw`	Capture/Compare 4 selection
8–9	2	CC4S	`rw`	Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER).
10	1	OC4FE	`rw`	Output compare 4 fast enable
10–11	2	IC4PSC	`rw`	Input capture 4 prescaler
11	1	OC4PE	`rw`	Output compare 4 preload enable
12–14	3	OC4M	`rw`	Output compare 4 mode
12–15	4	IC4F	`rw`	Input capture 4 filter
15	1	OC4CE	`rw`	Output compare 4 clear enable
16	1	OC3M_3	`rw`	Output compare 3 mode, bit 3
24	1	OC4M_3	`rw`	Output compare 4 mode, bit 3

Rejestr: CCER 0x40012C20

capture/compare enable register

Bit	Szer.	Pole	Dostęp	Opis
0	1	CC1E	`rw`	Capture/Compare 1 output enable
1	1	CC1P	`rw`	Capture/Compare 1 output Polarity
2	1	CC1NE	`rw`	Capture/Compare 1 complementary output enable
3	1	CC1NP	`rw`	Capture/Compare 1 output Polarity
4	1	CC2E	`rw`	Capture/Compare 2 output enable
5	1	CC2P	`rw`	Capture/Compare 2 output Polarity
6	1	CC2NE	`rw`	Capture/Compare 2 complementary output enable
7	1	CC2NP	`rw`	Capture/Compare 2 output Polarity
8	1	CC3E	`rw`	Capture/Compare 3 output enable
9	1	CC3P	`rw`	Capture/Compare 3 output Polarity
10	1	CC3NE	`rw`	Capture/Compare 3 complementary output enable
11	1	CC3NP	`rw`	Capture/Compare 3 output Polarity
12	1	CC4E	`rw`	Capture/Compare 4 output enable
13	1	CC4P	`rw`	Capture/Compare 4 output Polarity
15	1	CC4NP	`rw`	Capture/Compare 4 output Polarity
16	1	CC5E	`rw`	Capture/Compare 5 output enable
17	1	CC5P	`rw`	Capture/Compare 5 output Polarity
20	1	CC6E	`rw`	Capture/Compare 6 output enable
21	1	CC6P	`rw`	Capture/Compare 6 output Polarity

Rejestr: CNT16 0x40012C24

16-bit counter register

Brak zdefiniowanych pól bitowych.

Rejestr: CNT: 0x40012C24

counter

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	CNT	`rw`	Counter value
0–15	16	CNT	`rw`	counter value
31	1	UIFCPY	`ro`	UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0.

Rejestr: PSC 0x40012C28

prescaler

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	PSC	`rw`	Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in 'reset mode').

Rejestr: ARR 0x40012C2C

auto-reload register

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	ARR	`rw`	Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null.

Rejestr: RCR 0x40012C30

repetition counter register

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	REP:	—	Repetition counter value

Rejestr: CCR1 0x40012C34

capture/compare register

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	CCR:	—	Capture/Compare value

Rejestr: CCR2 0x40012C38

capture/compare register

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	CCR:	—	Capture/Compare value

Rejestr: CCR3 0x40012C3C

capture/compare register

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	CCR:	—	Capture/Compare value

Rejestr: CCR4 0x40012C40

capture/compare register

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	CCR:	—	Capture/Compare value

Rejestr: BDTR 0x40012C44

break and dead-time register

Bit	Szer.	Pole	Dostęp	Opis
0–7	8	DTG	`rw`	Dead-time generator setup
8–9	2	LOCK	`rw`	Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
10	1	OSSI	`rw`	Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
11	1	OSSR	`rw`	Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
12	1	BKE	`rw`	Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per ). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
13	1	BKP	`rw`	Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
14	1	AOE	`rw`	Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
15	1	MOE	`rw`	Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A).
16–19	4	BKF	`rw`	Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
20–23	4	BK2F	`rw`	Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
24	1	BK2E	`rw`	Break 2 enable Note: The BRK2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
25	1	BK2P	`rw`	Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
26	1	BKDSRM	`rw`	Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
27	1	BK2DSRM	`rw`	Break2 Disarm Refer to BKDSRM description
28	1	BKBID	`rw`	Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
29	1	BK2BID	`rw`	Break2 bidirectional Refer to BKBID description

Rejestr: DCR 0x40012C48

DMA control register

Bit	Szer.	Pole	Dostęp	Opis
0–4	5	DBA	`rw`	DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ...
8–12	5	DBL	`rw`	DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1. If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA.

Rejestr: DMAR 0x40012C4C

DMA address for full transfer

Bit	Szer.	Pole	Dostęp	Opis
0–31	32	DMAB	`rw`	DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).

Rejestr: OR1 0x40012C50

option register 1

Bit	Szer.	Pole	Dostęp	Opis
0	1	OCREF_CLR	`rw`	Ocref_clr source selection This bit selects the ocref_clr input source.

Rejestr: CCMR3_Output 0x40012C54

capture/compare mode register 2 (output mode)

Bit	Szer.	Pole	Dostęp	Opis
2	1	OC5FE	—	Output compare 5 fast enable
3	1	OC5PE	—	Output compare 5 preload enable
4–6	3	OC5M	—	Output compare 5 mode
7	1	OC5CE	—	Output compare 5 clear enable
10	1	OC6FE	—	Output compare 6 fast enable
11	1	OC6PE	—	Output compare 6 preload enable
12–14	3	OC6M	—	Output compare 6 mode
15	1	OC6CE	—	Output compare 6 clear enable
16	1	OC5M_3	—	Output compare 5 mode, bit 3
24	1	OC6M_3	—	Output compare 6 mode, bit 3

Rejestr: CCR5 0x40012C58

capture/compare register

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	CCR	`rw`	Capture/Compare value
29	1	GC5C1	`rw`	Group Channel 5 and Channel 1 Distortion on Channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals.
30	1	GC5C2	`rw`	Group Channel 5 and Channel 2 Distortion on Channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals.
31	1	GC5C3	`rw`	Group Channel 5 and Channel 3 Distortion on Channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals.

Rejestr: CCR6 0x40012C5C

capture/compare register

Bit	Szer.	Pole	Dostęp	Opis
0–15	16	CCR:	—	Capture/Compare value

Rejestr: AF1 0x40012C60

DMA address for full transfer

Bit	Szer.	Pole	Dostęp	Opis
0	1	BKINE	`rw`	BRK BKIN input enable This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
1	1	BKCMP1E	`rw`	BRK COMP1 enable This bit enables the COMP1 for the timer's BRK input. COMP1 output is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
2	1	BKCMP2E	`rw`	BRK COMP2 enable This bit enables the COMP2 for the timer's BRK input. COMP2 output is 'ORed' with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
9	1	BKINP	`rw`	BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
10	1	BKCMP1P	`rw`	BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
11	1	BKCMP2P	`rw`	BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
14–17	4	ETRSEL	`rw`	ETR source selection These bits select the ETR input source. Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Rejestr: AF2 0x40012C64

DMA address for full transfer

Bit	Szer.	Pole	Dostęp	Opis
0	1	BK2INE	`rw`	BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timer's BRK2 input. BKIN2 input is 'ORed' with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
1	1	BK2CMP1E	`rw`	BRK2 COMP1 enable This bit enables the COMP1 for the timer's BRK2 input. COMP1 output is 'ORed' with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
2	1	BK2CMP2E	`rw`	BRK2 COMP2 enable This bit enables the COMP2 for the timer's BRK2 input. COMP2 output is 'ORed' with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
9	1	BK2INP	`rw`	BRK2 BKIN2 input polarity This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
10	1	BK2CMP1P	`rw`	BRK2 COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
11	1	BK2CMP2P	`rw`	BRK2 COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Rejestr: TISEL 0x40012C68

TIM1 timer input selection register

Bit	Szer.	Pole	Dostęp	Opis
0–3	4	TI1SEL	`rw`	selects TI1[0] to TI1[15] input Others: Reserved
8–11	4	TI2SEL	`rw`	selects TI2[0] to TI2[15] input Others: Reserved
16–19	4	TI3SEL	`rw`	selects TI3[0] to TI3[15] input Others: Reserved
24–27	4	TI4SEL	`rw`	selects TI4[0] to TI4[15] input Others: Reserved