System
RCC 0x40021000
23 rejestrów/klastrów w tym peryferium.
Rejestr: CR 0x40021000
rw
Clock control register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 8 | 1 | HSION: | — | HSI16 clock enable |
| 9 | 1 | HSIKERON: | — | HSI16 always enable for peripheral kernels |
| 10 | 1 | HSIRDY: | — | HSI16 clock ready flag |
| 11–13 | 3 | HSIDIV: | — | HSI16 clock division factor |
| 16 | 1 | HSEON: | — | HSE clock enable |
| 17 | 1 | HSERDY: | — | HSE clock ready flag |
| 18 | 1 | HSEBYP: | — | HSE crystal oscillator bypass |
| 19 | 1 | CSSON: | — | Clock security system enable |
| 24 | 1 | PLLON: | — | PLL enable |
| 25 | 1 | PLLRDY: | — | PLL clock ready flag |
Rejestr: ICSCR: 0x40021004
Internal clock sources calibration register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 0–7 | 8 | HSICAL | `ro` | HSI16 clock calibration |
| 8–14 | 7 | HSITRIM | `rw` | HSI16 clock trimming |
Rejestr: CFGR: 0x40021008
Clock configuration register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 0–2 | 3 | SW | `rw` | System clock switch |
| 3–5 | 3 | SWS | `ro` | System clock switch status |
| 8–11 | 4 | HPRE | `rw` | AHB prescaler |
| 12–14 | 3 | PPRE | `rw` | APB prescaler |
| 16–19 | 4 | MCO2SEL | `rw` | MCO2SEL |
| 20–23 | 4 | MCO2PRE | `rw` | MCO2PRE |
| 24–27 | 4 | MCOSEL | `rw` | Microcontroller clock output |
| 28–31 | 4 | MCOPRE | `ro` | Microcontroller clock output prescaler |
Rejestr: PLLCFGR 0x4002100C
rw
PLL configuration register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 0–1 | 2 | PLLSRC: | — | PLL input clock source |
| 4–6 | 3 | PLLM: | — | Division factor M of the PLL input clock divider |
| 8–15 | 8 | PLLN: | — | PLL frequency multiplication factor N |
| 16 | 1 | PLLPEN: | — | PLLPCLK clock output enable |
| 17–21 | 5 | PLLP: | — | PLL VCO division factor P for PLLPCLK clock output |
| 24 | 1 | PLLQEN: | — | PLLQCLK clock output enable |
| 25–27 | 3 | PLLQ: | — | PLL VCO division factor Q for PLLQCLK clock output |
| 28 | 1 | PLLREN: | — | PLLRCLK clock output enable |
| 29–31 | 3 | PLLR: | — | PLL VCO division factor R for PLLRCLK clock output |
Rejestr: CIER 0x40021018
rw
Clock interrupt enable register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 0 | 1 | LSIRDYIE: | — | LSI ready interrupt enable |
| 1 | 1 | LSERDYIE: | — | LSE ready interrupt enable |
| 3 | 1 | HSIRDYIE: | — | HSI ready interrupt enable |
| 4 | 1 | HSERDYIE: | — | HSE ready interrupt enable |
| 5 | 1 | PLLSYSRDYIE: | — | PLL ready interrupt enable |
Rejestr: CIFR 0x4002101C
ro
Clock interrupt flag register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 0 | 1 | LSIRDYF: | — | LSI ready interrupt flag |
| 1 | 1 | LSERDYF: | — | LSE ready interrupt flag |
| 3 | 1 | HSIRDYF: | — | HSI ready interrupt flag |
| 4 | 1 | HSERDYF: | — | HSE ready interrupt flag |
| 5 | 1 | PLLSYSRDYF: | — | PLL ready interrupt flag |
| 8 | 1 | CSSF: | — | Clock security system interrupt flag |
| 9 | 1 | LSECSSF: | — | LSE Clock security system interrupt flag |
Rejestr: CICR 0x40021020
wo
Clock interrupt clear register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 0 | 1 | LSIRDYC: | — | LSI ready interrupt clear |
| 1 | 1 | LSERDYC: | — | LSE ready interrupt clear |
| 3 | 1 | HSIRDYC: | — | HSI ready interrupt clear |
| 4 | 1 | HSERDYC: | — | HSE ready interrupt clear |
| 5 | 1 | PLLSYSRDYC: | — | PLL ready interrupt clear |
| 8 | 1 | CSSC: | — | Clock security system interrupt clear |
| 9 | 1 | LSECSSC: | — | LSE Clock security system interrupt clear |
Rejestr: IOPRSTR 0x40021024
rw
I/O port reset register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 0 | 1 | GPIOARST: | — | GPIOARST |
| 1 | 1 | GPIOBRST: | — | GPIOBRST |
| 2 | 1 | GPIOCRST: | — | GPIOCRST |
| 3 | 1 | GPIODRST: | — | GPIODRST |
| 4 | 1 | GPIOERST: | — | GPIOERST |
| 5 | 1 | GPIOFRST: | — | GPIOFRST |
Rejestr: AHBRSTR 0x40021028
rw
AHB peripheral reset register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 0 | 1 | DMA1RST: | — | DMA1 reset |
| 1 | 1 | DMA2RST: | — | DMA1 reset |
| 8 | 1 | FLASHRST: | — | FLITF reset |
| 12 | 1 | CRCRST: | — | CRC reset |
Rejestr: APBRSTR1 0x4002102C
rw
APB peripheral reset register 1
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 1 | 1 | TIM3RST: | — | TIM3 timer reset |
| 2 | 1 | TIM4RST: | — | TIM4 timer reset |
| 4 | 1 | TIM6RST: | — | TIM6 timer reset |
| 5 | 1 | TIM7RST: | — | TIM7 timer reset |
| 8 | 1 | USART5RST: | — | USART5RST |
| 9 | 1 | USART6RST: | — | USART6RST |
| 13 | 1 | USBRST: | — | USBRST |
| 14 | 1 | SPI2RST: | — | SPI2 reset |
| 15 | 1 | SPI3RST: | — | SPI3 reset |
| 17 | 1 | USART2RST: | — | USART2 reset |
| 18 | 1 | USART3RST: | — | USART3 reset |
| 19 | 1 | USART4RST: | — | USART4 reset |
| 21 | 1 | I2C1RST: | — | I2C1 reset |
| 22 | 1 | I2C2RST: | — | I2C2 reset |
| 23 | 1 | I2C3RST: | — | I2C3RST reset |
| 27 | 1 | DBGRST: | — | Debug support reset |
| 28 | 1 | PWRRST: | — | Power interface reset |
Rejestr: APBRSTR2 0x40021030
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APB peripheral reset register 2
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 0 | 1 | SYSCFGRST: | — | SYSCFG, COMP and VREFBUF reset |
| 11 | 1 | TIM1RST: | — | TIM1 timer reset |
| 12 | 1 | SPI1RST: | — | SPI1 reset |
| 14 | 1 | USART1RST: | — | USART1 reset |
| 15 | 1 | TIM14RST: | — | TIM14 timer reset |
| 16 | 1 | TIM15RST: | — | TIM15 timer reset |
| 17 | 1 | TIM16RST: | — | TIM16 timer reset |
| 18 | 1 | TIM17RST: | — | TIM17 timer reset |
| 20 | 1 | ADCRST: | — | ADC reset |
Rejestr: IOPENR 0x40021034
rw
GPIO clock enable register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 0 | 1 | GPIOAEN: | — | I/O port A clock enable during Sleep mode |
| 1 | 1 | GPIOBEN: | — | I/O port B clock enable during Sleep mode |
| 2 | 1 | GPIOCEN: | — | I/O port C clock enable during Sleep mode |
| 3 | 1 | GPIODEN: | — | I/O port D clock enable during Sleep mode |
| 4 | 1 | GPIOEEN: | — | I/O port E clock enable during Sleep mode |
| 5 | 1 | GPIOFEN: | — | I/O port F clock enable during Sleep mode |
Rejestr: AHBENR 0x40021038
rw
AHB peripheral clock enable register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 0 | 1 | DMA1EN: | — | DMA1 clock enable |
| 1 | 1 | DMA2EN: | — | DMA2 clock enable |
| 8 | 1 | FLASHEN: | — | Flash memory interface clock enable |
| 12 | 1 | CRCEN: | — | CRC clock enable |
Rejestr: APBENR1 0x4002103C
rw
APB peripheral clock enable register 1
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 1 | 1 | TIM3EN: | — | TIM3 timer clock enable |
| 2 | 1 | TIM4EN: | — | TIM4 timer clock enable |
| 4 | 1 | TIM6EN: | — | TIM6 timer clock enable |
| 5 | 1 | TIM7EN: | — | TIM7 timer clock enable |
| 8 | 1 | USART5EN: | — | USART5EN |
| 9 | 1 | USART6EN: | — | USART6EN |
| 10 | 1 | RTCAPBEN: | — | RTC APB clock enable |
| 11 | 1 | WWDGEN: | — | WWDG clock enable |
| 13 | 1 | USBEN: | — | USBEN |
| 14 | 1 | SPI2EN: | — | SPI2 clock enable |
| 15 | 1 | SPI3EN: | — | SPI3 clock enable |
| 17 | 1 | USART2EN: | — | USART2 clock enable |
| 18 | 1 | USART3EN: | — | USART3 clock enable |
| 19 | 1 | USART4EN: | — | USART4 clock enable |
| 21 | 1 | I2C1EN: | — | I2C1 clock enable |
| 22 | 1 | I2C2EN: | — | I2C2 clock enable |
| 23 | 1 | I2C3EN: | — | I2C3 clock enable |
| 27 | 1 | DBGEN: | — | Debug support clock enable |
| 28 | 1 | PWREN: | — | Power interface clock enable |
Rejestr: APBENR2 0x40021040
rw
APB peripheral clock enable register 2
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 0 | 1 | SYSCFGEN: | — | SYSCFG, COMP and VREFBUF clock enable |
| 11 | 1 | TIM1EN: | — | TIM1 timer clock enable |
| 12 | 1 | SPI1EN: | — | SPI1 clock enable |
| 14 | 1 | USART1EN: | — | USART1 clock enable |
| 15 | 1 | TIM14EN: | — | TIM14 timer clock enable |
| 16 | 1 | TIM15EN: | — | TIM15 timer clock enable |
| 17 | 1 | TIM16EN: | — | TIM16 timer clock enable |
| 18 | 1 | TIM17EN: | — | TIM16 timer clock enable |
| 20 | 1 | ADCEN: | — | ADC clock enable |
Rejestr: IOPSMENR 0x40021044
rw
GPIO in Sleep mode clock enable register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 0 | 1 | GPIOASMEN: | — | I/O port A clock enable during Sleep mode |
| 1 | 1 | GPIOBSMEN: | — | I/O port B clock enable during Sleep mode |
| 2 | 1 | GPIOCSMEN: | — | I/O port C clock enable during Sleep mode |
| 3 | 1 | GPIODSMEN: | — | I/O port D clock enable during Sleep mode |
| 4 | 1 | GPIOESMEN: | — | I/O port E clock enable during Sleep mode |
| 5 | 1 | GPIOFSMEN: | — | I/O port F clock enable during Sleep mode |
Rejestr: AHBSMENR 0x40021048
rw
AHB peripheral clock enable in Sleep mode register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 0 | 1 | DMA1SMEN: | — | DMA1 clock enable during Sleep mode |
| 1 | 1 | DMA2SMEN: | — | DMA2 clock enable during Sleep mode |
| 8 | 1 | FLASHSMEN: | — | Flash memory interface clock enable during Sleep mode |
| 9 | 1 | SRAMSMEN: | — | SRAM clock enable during Sleep mode |
| 12 | 1 | CRCSMEN: | — | CRC clock enable during Sleep mode |
Rejestr: APBSMENR1 0x4002104C
rw
APB peripheral clock enable in Sleep mode register 1
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 1 | 1 | TIM3SMEN: | — | TIM3 timer clock enable during Sleep mode |
| 2 | 1 | TIM4SMEN: | — | TIM4 timer clock enable during Sleep mode |
| 4 | 1 | TIM6SMEN: | — | TIM6 timer clock enable during Sleep mode |
| 5 | 1 | TIM7SMEN: | — | TIM7 timer clock enable during Sleep mode |
| 8 | 1 | USART5SMEN: | — | USART5 clock enable |
| 9 | 1 | USART6SMEN: | — | USART6 clock enable |
| 10 | 1 | RTCAPBSMEN: | — | RTC APB clock enable during Sleep mode |
| 11 | 1 | WWDGSMEN: | — | WWDG clock enable during Sleep mode |
| 13 | 1 | USBSMEN: | — | USB clock enable during Sleep mode |
| 14 | 1 | SPI2SMEN: | — | SPI2 clock enable during Sleep mode |
| 15 | 1 | SPI3SMEN: | — | SPI3 clock enable during Sleep mode |
| 17 | 1 | USART2SMEN: | — | USART2 clock enable during Sleep mode |
| 18 | 1 | USART3SMEN: | — | USART3 clock enable during Sleep mode |
| 19 | 1 | USART4SMEN: | — | USART4 clock enable during Sleep mode |
| 21 | 1 | I2C1SMEN: | — | I2C1 clock enable during Sleep mode |
| 22 | 1 | I2C2SMEN: | — | I2C2 clock enable during Sleep mode |
| 23 | 1 | I2C3SMEN: | — | I2C3 clock enable during Sleep mode |
| 27 | 1 | DBGSMEN: | — | Debug support clock enable during Sleep mode |
| 28 | 1 | PWRSMEN: | — | Power interface clock enable during Sleep mode |
Rejestr: APBSMENR2 0x40021050
rw
APB peripheral clock enable in Sleep mode register 2
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 0 | 1 | SYSCFGSMEN: | — | SYSCFG, COMP and VREFBUF clock enable during Sleep mode |
| 11 | 1 | TIM1SMEN: | — | TIM1 timer clock enable during Sleep mode |
| 12 | 1 | SPI1SMEN: | — | SPI1 clock enable during Sleep mode |
| 14 | 1 | USART1SMEN: | — | USART1 clock enable during Sleep mode |
| 15 | 1 | TIM14SMEN: | — | TIM14 timer clock enable during Sleep mode |
| 16 | 1 | TIM15SMEN: | — | TIM15 timer clock enable during Sleep mode |
| 17 | 1 | TIM16SMEN: | — | TIM16 timer clock enable during Sleep mode |
| 18 | 1 | TIM17SMEN: | — | TIM16 timer clock enable during Sleep mode |
| 20 | 1 | ADCSMEN: | — | ADC clock enable during Sleep mode |
Rejestr: CCIPR 0x40021054
rw
Peripherals independent clock configuration register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 0–1 | 2 | USART1SEL: | — | USART1 clock source selection |
| 2–3 | 2 | USART2SEL: | — | USART2 clock source selection |
| 4–5 | 2 | USART3SEL: | — | USART3 clock source selection |
| 12–13 | 2 | I2C1SEL: | — | I2C1 clock source selection |
| 14–15 | 2 | I2C2SEL: | — | I2S1 clock source selection |
| 22 | 1 | TIM1SEL: | — | TIM1 clock source selection |
| 24 | 1 | TIM15SEL: | — | TIM15 clock source selection |
| 30–31 | 2 | ADCSEL: | — | ADCs clock source selection |
Rejestr: CCIPR2 0x40021058
rw
Peripherals independent clock configuration register 2
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 0–1 | 2 | I2S1SEL: | — | 2S1SEL |
| 2–3 | 2 | I2S2SEL: | — | I2S2SEL |
| 12–13 | 2 | USBSEL: | — | USBSEL |
Rejestr: BDCR 0x4002105C
rw
RTC domain control register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 0 | 1 | LSEON: | — | LSE oscillator enable |
| 1 | 1 | LSERDY | `ro` | LSE oscillator ready |
| 2 | 1 | LSEBYP: | — | LSE oscillator bypass |
| 3–4 | 2 | LSEDRV: | — | LSE oscillator drive capability |
| 5 | 1 | LSECSSON: | — | CSS on LSE enable |
| 6 | 1 | LSECSSD | `ro` | CSS on LSE failure Detection |
| 8–9 | 2 | RTCSEL: | — | RTC clock source selection |
| 15 | 1 | RTCEN: | — | RTC clock enable |
| 16 | 1 | BDRST: | — | RTC domain software reset |
| 24 | 1 | LSCOEN: | — | Low-speed clock output (LSCO) enable |
| 25 | 1 | LSCOSEL: | — | Low-speed clock output selection |
Rejestr: CSR 0x40021060
rw
Control/status register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|
| 0 | 1 | LSION: | — | LSI oscillator enable |
| 1 | 1 | LSIRDY | `ro` | LSI oscillator ready |
| 23 | 1 | RMVF: | — | Remove reset flags |
| 25 | 1 | OBLRSTF | `ro` | Option byte loader reset flag |
| 26 | 1 | PINRSTF | `ro` | Pin reset flag |
| 27 | 1 | PWRRSTF | `ro` | BOR or POR/PDR flag |
| 28 | 1 | SFTRSTF | `ro` | Software reset flag |
| 29 | 1 | IWDGRSTF | `ro` | Independent window watchdog reset flag |
| 30 | 1 | WWDGRSTF | `ro` | Window watchdog reset flag |
| 31 | 1 | LPWRRSTF | `ro` | Low-power reset flag |