System

DBG 0x40015800

4 rejestrów/klastrów w tym peryferium.

Rejestr: IDCODE 0x40015800

ro

MCU Device ID Code Register

Bit	Szer.	Pole	Dostęp	Opis
0–11	12	DEV_ID:	—	Device Identifier
16–31	16	REV_ID:	—	Revision Identifier

Rejestr: CR 0x40015804

rw

DBG configuration register

Bit	Szer.	Pole	Dostęp	Opis
1	1	DBG_STOP	`rw`	Debug Stop mode Debug options in Stop mode. Upon Stop mode exit, the software must re-establish the desired clock configuration.
2	1	DBG_STANDBY	`rw`	Debug Standby and Shutdown modes Debug options in Standby or Shutdown mode.

Rejestr: APB_FZ1 0x40015808

rw

DBG APB freeze register 1

Bit	Szer.	Pole	Dostęp	Opis
0	1	DBG_TIM2_STOP	`rw`	Clocking of TIM2 counter when the core is halted This bit enables/disables the clock to the counter of TIM2 when the core is halted:
1	1	DBG_TIM3_STOP	`rw`	Clocking of TIM3 counter when the core is halted This bit enables/disables the clock to the counter of TIM3 when the core is halted:
4	1	DBG_TIM6_STOP	`rw`	Clocking of TIM6 counter when the core is halted This bit enables/disables the clock to the counter of TIM6 when the core is halted:
5	1	DBG_TIM7_STOP	`rw`	Clocking of TIM7 counter when the core is halted. This bit enables/disables the clock to the counter of ITIM7 when the core is halted:
10	1	DBG_RTC_STOP	`rw`	Clocking of RTC counter when the core is halted This bit enables/disables the clock to the counter of RTC when the core is halted:
11	1	DBG_WWDG_STOP	`rw`	Clocking of WWDG counter when the core is halted This bit enables/disables the clock to the counter of WWDG when the core is halted:
12	1	DBG_IWDG_STOP	`rw`	Clocking of IWDG counter when the core is halted This bit enables/disables the clock to the counter of IWDG when the core is halted:
21	1	DBG_I2C1_SMBUS_TIMEOUT	`rw`	SMBUS timeout when core is halted
30	1	DBG_LPTIM2_STOP	`rw`	Clocking of LPTIMER2 counter when the core is halted This bit enables/disables the clock to the counter of LPTIMER2 when the core is halted:
31	1	DBG_LPTIM1_STOP	`rw`	Clocking of LPTIMER1 counter when the core is halted This bit enables/disables the clock to the counter of LPTIMER1 when the core is halted:

Rejestr: APB_FZ2 0x4001580C

rw

DBG APB freeze register 2

Bit	Szer.	Pole	Dostęp	Opis
11	1	DBG_TIM1_STOP	`rw`	Clocking of TIM1 counter when the core is halted This bit enables/disables the clock to the counter of TIM1 when the core is halted:
15	1	DBG_TIM14_STOP	`rw`	Clocking of TIM14 counter when the core is halted This bit enables/disables the clock to the counter of TIM14 when the core is halted:
16	1	DBG_TIM15_STOP	`rw`	Clocking of TIM15 counter when the core is halted This bit enables/disables the clock to the counter of TIM15 when the core is halted: Only available on STM32G071xx and STM32G081xx, reserved on STM32G031xx and STM32G041xx.
17	1	DBG_TIM16_STOP	`rw`	Clocking of TIM16 counter when the core is halted This bit enables/disables the clock to the counter of TIM16 when the core is halted:
18	1	DBG_TIM17_STOP	`rw`	Clocking of TIM17 counter when the core is halted This bit enables/disables the clock to the counter of TIM17 when the core is halted: