DMA

DMA1 0x40020000

37 rejestrów/klastrów w tym peryferium.

Rejestr: ISR:  0x40020000

DMA interrupt status register

Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: TEIF7Bit 26: HTIF7Bit 25: TCIF7Bit 24: GIF724Bit 23: TEIF6Bit 22: HTIF6Bit 21: TCIF6Bit 20: GIF620Bit 19: TEIF5Bit 18: HTIF5Bit 17: TCIF5Bit 16: GIF516Bit 15: TEIF4Bit 14: HTIF4Bit 13: TCIF4Bit 12: GIF412Bit 11: TEIF3Bit 10: HTIF3Bit 9: TCIF3Bit 8: GIF38Bit 7: TEIF2Bit 6: HTIF2Bit 5: TCIF2Bit 4: GIF24Bit 3: TEIF1Bit 2: HTIF1Bit 1: TCIF1Bit 0: GIF10
BitSzer.PoleDostępOpis
01GIF1`ro`Channel 1 Global interrupt flag
11TCIF1`ro`Channel 1 Transfer Complete flag
21HTIF1`ro`Channel 1 Half Transfer Complete flag
31TEIF1`ro`Channel 1 Transfer Error flag
41GIF2`ro`Channel 2 Global interrupt flag
51TCIF2`ro`Channel 2 Transfer Complete flag
61HTIF2`ro`Channel 2 Half Transfer Complete flag
71TEIF2`ro`Channel 2 Transfer Error flag
81GIF3`ro`Channel 3 Global interrupt flag
91TCIF3`ro`Channel 3 Transfer Complete flag
101HTIF3`ro`Channel 3 Half Transfer Complete flag
111TEIF3`ro`Channel 3 Transfer Error flag
121GIF4`ro`Channel 4 Global interrupt flag
131TCIF4`ro`Channel 4 Transfer Complete flag
141HTIF4`ro`Channel 4 Half Transfer Complete flag
151TEIF4`ro`Channel 4 Transfer Error flag
161GIF5`ro`Channel 5 Global interrupt flag
171TCIF5`ro`Channel 5 Transfer Complete flag
181HTIF5`ro`Channel 5 Half Transfer Complete flag
191TEIF5`ro`Channel 5 Transfer Error flag
201GIF6`ro`Channel 6 Global interrupt flag
211TCIF6`ro`Channel 6 Transfer Complete flag
221HTIF6`ro`Channel 6 Half Transfer Complete flag
231TEIF6`ro`Channel 6 Transfer Error flag
241GIF7`ro`Channel 7 Global interrupt flag
251TCIF7`ro`Channel 7 Transfer Complete flag
261HTIF7`ro`Channel 7 Half Transfer Complete flag
271TEIF7`ro`Channel 7 Transfer Error flag
Rejestr: IFCR:  0x40020004

DMA interrupt flag clear register

Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: CTEIF7Bit 26: CHTIF7Bit 25: CTCIF7Bit 24: CGIF724Bit 23: CTEIF6Bit 22: CHTIF6Bit 21: CTCIF6Bit 20: CGIF620Bit 19: CTEIF5Bit 18: CHTIF5Bit 17: CTCIF5Bit 16: CGIF516Bit 15: CTEIF4Bit 14: CHTIF4Bit 13: CTCIF4Bit 12: CGIF412Bit 11: CTEIF3Bit 10: CHTIF3Bit 9: CTCIF3Bit 8: CGIF38Bit 7: CTEIF2Bit 6: CHTIF2Bit 5: CTCIF2Bit 4: CGIF24Bit 3: CTEIF1Bit 2: CHTIF1Bit 1: CTCIF1Bit 0: CGIF10
BitSzer.PoleDostępOpis
01CGIF1`wo`Channel 1 Global interrupt clear
11CTCIF1`wo`Channel 1 Transfer Complete clear
21CHTIF1`wo`Channel 1 Half Transfer clear
31CTEIF1`wo`Channel 1 Transfer Error clear
41CGIF2`wo`Channel 2 Global interrupt clear
51CTCIF2`wo`Channel 2 Transfer Complete clear
61CHTIF2`wo`Channel 2 Half Transfer clear
71CTEIF2`wo`Channel 2 Transfer Error clear
81CGIF3`wo`Channel 3 Global interrupt clear
91CTCIF3`wo`Channel 3 Transfer Complete clear
101CHTIF3`wo`Channel 3 Half Transfer clear
111CTEIF3`wo`Channel 3 Transfer Error clear
121CGIF4`wo`Channel 4 Global interrupt clear
131CTCIF4`wo`Channel 4 Transfer Complete clear
141CHTIF4`wo`Channel 4 Half Transfer clear
151CTEIF4`wo`Channel 4 Transfer Error clear
161CGIF5`wo`Channel 5 Global interrupt clear
171CTCIF5`wo`Channel 5 Transfer Complete clear
181CHTIF5`wo`Channel 5 Half Transfer clear
191CTEIF5`wo`Channel 5 Transfer Error clear
201CGIF6`wo`Channel 6 Global interrupt clear
211CTCIF6`wo`Channel 6 Transfer Complete clear
221CHTIF6`wo`Channel 6 Half Transfer clear
231CTEIF6`wo`Channel 6 Transfer Error clear
241CGIF7`wo`Channel 7 Global interrupt clear
251CTCIF7`wo`Channel 7 Transfer Complete clear
261CHTIF7`wo`Channel 7 Half Transfer clear
271CTEIF7`wo`Channel 7 Transfer Error clear
Klaster: CH1  0x40020008

Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers

Brak zdefiniowanych pól bitowych.

Rejestr: CR1:  0x40020008

DMA channel 1 configuration register

Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: zarezerwowanyBit 14: MEM2MEMBit 13: PLBit 12: PL12Bit 11: MSIZEBit 10: MSIZEBit 9: PSIZEBit 8: PSIZE8Bit 7: MINCBit 6: PINCBit 5: CIRCBit 4: DIR4Bit 3: TEIEBit 2: HTIEBit 1: TCIEBit 0: EN0
BitSzer.PoleDostępOpis
01EN`rw`channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software.
11TCIE`rw`transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
21HTIE`rw`half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
31TEIE`rw`transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
41DIR`rw`data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
51CIRC`rw`circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
61PINC`rw`peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
71MINC`rw`memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
8–92PSIZE`rw`peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
10–112MSIZE`rw`memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
12–132PL`rw`priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
141MEM2MEM`rw`memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
Rejestr: NDTR1:  0x4002000C

DMA channel x number of data register

Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: NDTBit 14: NDTBit 13: NDTBit 12: NDT12Bit 11: NDTBit 10: NDTBit 9: NDTBit 8: NDT8Bit 7: NDTBit 6: NDTBit 5: NDTBit 4: NDT4Bit 3: NDTBit 2: NDTBit 1: NDTBit 0: NDT0
BitSzer.PoleDostępOpis
0–1516NDT`rw`number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
Rejestr: PAR1:  0x40020010

DMA channel x peripheral address register

Bit 31: PA31Bit 30: PABit 29: PABit 28: PA28Bit 27: PABit 26: PABit 25: PABit 24: PA24Bit 23: PABit 22: PABit 21: PABit 20: PA20Bit 19: PABit 18: PABit 17: PABit 16: PA16Bit 15: PABit 14: PABit 13: PABit 12: PA12Bit 11: PABit 10: PABit 9: PABit 8: PA8Bit 7: PABit 6: PABit 5: PABit 4: PA4Bit 3: PABit 2: PABit 1: PABit 0: PA0
BitSzer.PoleDostępOpis
0–3132PA`rw`peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
Rejestr: MAR1:  0x40020014

DMA channel x memory address register

Bit 31: MA31Bit 30: MABit 29: MABit 28: MA28Bit 27: MABit 26: MABit 25: MABit 24: MA24Bit 23: MABit 22: MABit 21: MABit 20: MA20Bit 19: MABit 18: MABit 17: MABit 16: MA16Bit 15: MABit 14: MABit 13: MABit 12: MA12Bit 11: MABit 10: MABit 9: MABit 8: MA8Bit 7: MABit 6: MABit 5: MABit 4: MA4Bit 3: MABit 2: MABit 1: MABit 0: MA0
BitSzer.PoleDostępOpis
0–3132MA`rw`peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
Klaster: CH2  0x4002001C

Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers

Brak zdefiniowanych pól bitowych.

Rejestr: CR2:  0x4002001C

DMA channel 1 configuration register

Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: zarezerwowanyBit 14: MEM2MEMBit 13: PLBit 12: PL12Bit 11: MSIZEBit 10: MSIZEBit 9: PSIZEBit 8: PSIZE8Bit 7: MINCBit 6: PINCBit 5: CIRCBit 4: DIR4Bit 3: TEIEBit 2: HTIEBit 1: TCIEBit 0: EN0
BitSzer.PoleDostępOpis
01EN`rw`channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software.
11TCIE`rw`transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
21HTIE`rw`half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
31TEIE`rw`transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
41DIR`rw`data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
51CIRC`rw`circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
61PINC`rw`peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
71MINC`rw`memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
8–92PSIZE`rw`peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
10–112MSIZE`rw`memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
12–132PL`rw`priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
141MEM2MEM`rw`memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
Rejestr: NDTR2:  0x40020020

DMA channel x number of data register

Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: NDTBit 14: NDTBit 13: NDTBit 12: NDT12Bit 11: NDTBit 10: NDTBit 9: NDTBit 8: NDT8Bit 7: NDTBit 6: NDTBit 5: NDTBit 4: NDT4Bit 3: NDTBit 2: NDTBit 1: NDTBit 0: NDT0
BitSzer.PoleDostępOpis
0–1516NDT`rw`number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
Rejestr: PAR2:  0x40020024

DMA channel x peripheral address register

Bit 31: PA31Bit 30: PABit 29: PABit 28: PA28Bit 27: PABit 26: PABit 25: PABit 24: PA24Bit 23: PABit 22: PABit 21: PABit 20: PA20Bit 19: PABit 18: PABit 17: PABit 16: PA16Bit 15: PABit 14: PABit 13: PABit 12: PA12Bit 11: PABit 10: PABit 9: PABit 8: PA8Bit 7: PABit 6: PABit 5: PABit 4: PA4Bit 3: PABit 2: PABit 1: PABit 0: PA0
BitSzer.PoleDostępOpis
0–3132PA`rw`peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
Rejestr: MAR2:  0x40020028

DMA channel x memory address register

Bit 31: MA31Bit 30: MABit 29: MABit 28: MA28Bit 27: MABit 26: MABit 25: MABit 24: MA24Bit 23: MABit 22: MABit 21: MABit 20: MA20Bit 19: MABit 18: MABit 17: MABit 16: MA16Bit 15: MABit 14: MABit 13: MABit 12: MA12Bit 11: MABit 10: MABit 9: MABit 8: MA8Bit 7: MABit 6: MABit 5: MABit 4: MA4Bit 3: MABit 2: MABit 1: MABit 0: MA0
BitSzer.PoleDostępOpis
0–3132MA`rw`peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
Klaster: CH3  0x40020030

Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers

Brak zdefiniowanych pól bitowych.

Rejestr: CR3:  0x40020030

DMA channel 1 configuration register

Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: zarezerwowanyBit 14: MEM2MEMBit 13: PLBit 12: PL12Bit 11: MSIZEBit 10: MSIZEBit 9: PSIZEBit 8: PSIZE8Bit 7: MINCBit 6: PINCBit 5: CIRCBit 4: DIR4Bit 3: TEIEBit 2: HTIEBit 1: TCIEBit 0: EN0
BitSzer.PoleDostępOpis
01EN`rw`channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software.
11TCIE`rw`transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
21HTIE`rw`half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
31TEIE`rw`transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
41DIR`rw`data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
51CIRC`rw`circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
61PINC`rw`peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
71MINC`rw`memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
8–92PSIZE`rw`peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
10–112MSIZE`rw`memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
12–132PL`rw`priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
141MEM2MEM`rw`memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
Rejestr: NDTR3:  0x40020034

DMA channel x number of data register

Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: NDTBit 14: NDTBit 13: NDTBit 12: NDT12Bit 11: NDTBit 10: NDTBit 9: NDTBit 8: NDT8Bit 7: NDTBit 6: NDTBit 5: NDTBit 4: NDT4Bit 3: NDTBit 2: NDTBit 1: NDTBit 0: NDT0
BitSzer.PoleDostępOpis
0–1516NDT`rw`number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
Rejestr: PAR3:  0x40020038

DMA channel x peripheral address register

Bit 31: PA31Bit 30: PABit 29: PABit 28: PA28Bit 27: PABit 26: PABit 25: PABit 24: PA24Bit 23: PABit 22: PABit 21: PABit 20: PA20Bit 19: PABit 18: PABit 17: PABit 16: PA16Bit 15: PABit 14: PABit 13: PABit 12: PA12Bit 11: PABit 10: PABit 9: PABit 8: PA8Bit 7: PABit 6: PABit 5: PABit 4: PA4Bit 3: PABit 2: PABit 1: PABit 0: PA0
BitSzer.PoleDostępOpis
0–3132PA`rw`peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
Rejestr: MAR3:  0x4002003C

DMA channel x memory address register

Bit 31: MA31Bit 30: MABit 29: MABit 28: MA28Bit 27: MABit 26: MABit 25: MABit 24: MA24Bit 23: MABit 22: MABit 21: MABit 20: MA20Bit 19: MABit 18: MABit 17: MABit 16: MA16Bit 15: MABit 14: MABit 13: MABit 12: MA12Bit 11: MABit 10: MABit 9: MABit 8: MA8Bit 7: MABit 6: MABit 5: MABit 4: MA4Bit 3: MABit 2: MABit 1: MABit 0: MA0
BitSzer.PoleDostępOpis
0–3132MA`rw`peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
Klaster: CH4  0x40020044

Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers

Brak zdefiniowanych pól bitowych.

Rejestr: CR4:  0x40020044

DMA channel 1 configuration register

Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: zarezerwowanyBit 14: MEM2MEMBit 13: PLBit 12: PL12Bit 11: MSIZEBit 10: MSIZEBit 9: PSIZEBit 8: PSIZE8Bit 7: MINCBit 6: PINCBit 5: CIRCBit 4: DIR4Bit 3: TEIEBit 2: HTIEBit 1: TCIEBit 0: EN0
BitSzer.PoleDostępOpis
01EN`rw`channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software.
11TCIE`rw`transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
21HTIE`rw`half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
31TEIE`rw`transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
41DIR`rw`data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
51CIRC`rw`circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
61PINC`rw`peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
71MINC`rw`memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
8–92PSIZE`rw`peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
10–112MSIZE`rw`memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
12–132PL`rw`priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
141MEM2MEM`rw`memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
Rejestr: NDTR4:  0x40020048

DMA channel x number of data register

Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: NDTBit 14: NDTBit 13: NDTBit 12: NDT12Bit 11: NDTBit 10: NDTBit 9: NDTBit 8: NDT8Bit 7: NDTBit 6: NDTBit 5: NDTBit 4: NDT4Bit 3: NDTBit 2: NDTBit 1: NDTBit 0: NDT0
BitSzer.PoleDostępOpis
0–1516NDT`rw`number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
Rejestr: PAR4:  0x4002004C

DMA channel x peripheral address register

Bit 31: PA31Bit 30: PABit 29: PABit 28: PA28Bit 27: PABit 26: PABit 25: PABit 24: PA24Bit 23: PABit 22: PABit 21: PABit 20: PA20Bit 19: PABit 18: PABit 17: PABit 16: PA16Bit 15: PABit 14: PABit 13: PABit 12: PA12Bit 11: PABit 10: PABit 9: PABit 8: PA8Bit 7: PABit 6: PABit 5: PABit 4: PA4Bit 3: PABit 2: PABit 1: PABit 0: PA0
BitSzer.PoleDostępOpis
0–3132PA`rw`peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
Rejestr: MAR4:  0x40020050

DMA channel x memory address register

Bit 31: MA31Bit 30: MABit 29: MABit 28: MA28Bit 27: MABit 26: MABit 25: MABit 24: MA24Bit 23: MABit 22: MABit 21: MABit 20: MA20Bit 19: MABit 18: MABit 17: MABit 16: MA16Bit 15: MABit 14: MABit 13: MABit 12: MA12Bit 11: MABit 10: MABit 9: MABit 8: MA8Bit 7: MABit 6: MABit 5: MABit 4: MA4Bit 3: MABit 2: MABit 1: MABit 0: MA0
BitSzer.PoleDostępOpis
0–3132MA`rw`peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
Klaster: CH5  0x40020058

Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers

Brak zdefiniowanych pól bitowych.

Rejestr: CR5:  0x40020058

DMA channel 1 configuration register

Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: zarezerwowanyBit 14: MEM2MEMBit 13: PLBit 12: PL12Bit 11: MSIZEBit 10: MSIZEBit 9: PSIZEBit 8: PSIZE8Bit 7: MINCBit 6: PINCBit 5: CIRCBit 4: DIR4Bit 3: TEIEBit 2: HTIEBit 1: TCIEBit 0: EN0
BitSzer.PoleDostępOpis
01EN`rw`channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software.
11TCIE`rw`transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
21HTIE`rw`half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
31TEIE`rw`transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
41DIR`rw`data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
51CIRC`rw`circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
61PINC`rw`peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
71MINC`rw`memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
8–92PSIZE`rw`peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
10–112MSIZE`rw`memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
12–132PL`rw`priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
141MEM2MEM`rw`memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
Rejestr: NDTR5:  0x4002005C

DMA channel x number of data register

Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: NDTBit 14: NDTBit 13: NDTBit 12: NDT12Bit 11: NDTBit 10: NDTBit 9: NDTBit 8: NDT8Bit 7: NDTBit 6: NDTBit 5: NDTBit 4: NDT4Bit 3: NDTBit 2: NDTBit 1: NDTBit 0: NDT0
BitSzer.PoleDostępOpis
0–1516NDT`rw`number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
Rejestr: PAR5:  0x40020060

DMA channel x peripheral address register

Bit 31: PA31Bit 30: PABit 29: PABit 28: PA28Bit 27: PABit 26: PABit 25: PABit 24: PA24Bit 23: PABit 22: PABit 21: PABit 20: PA20Bit 19: PABit 18: PABit 17: PABit 16: PA16Bit 15: PABit 14: PABit 13: PABit 12: PA12Bit 11: PABit 10: PABit 9: PABit 8: PA8Bit 7: PABit 6: PABit 5: PABit 4: PA4Bit 3: PABit 2: PABit 1: PABit 0: PA0
BitSzer.PoleDostępOpis
0–3132PA`rw`peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
Rejestr: MAR5:  0x40020064

DMA channel x memory address register

Bit 31: MA31Bit 30: MABit 29: MABit 28: MA28Bit 27: MABit 26: MABit 25: MABit 24: MA24Bit 23: MABit 22: MABit 21: MABit 20: MA20Bit 19: MABit 18: MABit 17: MABit 16: MA16Bit 15: MABit 14: MABit 13: MABit 12: MA12Bit 11: MABit 10: MABit 9: MABit 8: MA8Bit 7: MABit 6: MABit 5: MABit 4: MA4Bit 3: MABit 2: MABit 1: MABit 0: MA0
BitSzer.PoleDostępOpis
0–3132MA`rw`peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
Klaster: CH6  0x4002006C

Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers

Brak zdefiniowanych pól bitowych.

Rejestr: CR6:  0x4002006C

DMA channel 1 configuration register

Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: zarezerwowanyBit 14: MEM2MEMBit 13: PLBit 12: PL12Bit 11: MSIZEBit 10: MSIZEBit 9: PSIZEBit 8: PSIZE8Bit 7: MINCBit 6: PINCBit 5: CIRCBit 4: DIR4Bit 3: TEIEBit 2: HTIEBit 1: TCIEBit 0: EN0
BitSzer.PoleDostępOpis
01EN`rw`channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software.
11TCIE`rw`transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
21HTIE`rw`half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
31TEIE`rw`transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
41DIR`rw`data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
51CIRC`rw`circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
61PINC`rw`peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
71MINC`rw`memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
8–92PSIZE`rw`peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
10–112MSIZE`rw`memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
12–132PL`rw`priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
141MEM2MEM`rw`memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
Rejestr: NDTR6:  0x40020070

DMA channel x number of data register

Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: NDTBit 14: NDTBit 13: NDTBit 12: NDT12Bit 11: NDTBit 10: NDTBit 9: NDTBit 8: NDT8Bit 7: NDTBit 6: NDTBit 5: NDTBit 4: NDT4Bit 3: NDTBit 2: NDTBit 1: NDTBit 0: NDT0
BitSzer.PoleDostępOpis
0–1516NDT`rw`number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
Rejestr: PAR6:  0x40020074

DMA channel x peripheral address register

Bit 31: PA31Bit 30: PABit 29: PABit 28: PA28Bit 27: PABit 26: PABit 25: PABit 24: PA24Bit 23: PABit 22: PABit 21: PABit 20: PA20Bit 19: PABit 18: PABit 17: PABit 16: PA16Bit 15: PABit 14: PABit 13: PABit 12: PA12Bit 11: PABit 10: PABit 9: PABit 8: PA8Bit 7: PABit 6: PABit 5: PABit 4: PA4Bit 3: PABit 2: PABit 1: PABit 0: PA0
BitSzer.PoleDostępOpis
0–3132PA`rw`peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
Rejestr: MAR6:  0x40020078

DMA channel x memory address register

Bit 31: MA31Bit 30: MABit 29: MABit 28: MA28Bit 27: MABit 26: MABit 25: MABit 24: MA24Bit 23: MABit 22: MABit 21: MABit 20: MA20Bit 19: MABit 18: MABit 17: MABit 16: MA16Bit 15: MABit 14: MABit 13: MABit 12: MA12Bit 11: MABit 10: MABit 9: MABit 8: MA8Bit 7: MABit 6: MABit 5: MABit 4: MA4Bit 3: MABit 2: MABit 1: MABit 0: MA0
BitSzer.PoleDostępOpis
0–3132MA`rw`peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
Klaster: CH7  0x40020080

Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers

Brak zdefiniowanych pól bitowych.

Rejestr: CR7:  0x40020080

DMA channel 1 configuration register

Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: zarezerwowanyBit 14: MEM2MEMBit 13: PLBit 12: PL12Bit 11: MSIZEBit 10: MSIZEBit 9: PSIZEBit 8: PSIZE8Bit 7: MINCBit 6: PINCBit 5: CIRCBit 4: DIR4Bit 3: TEIEBit 2: HTIEBit 1: TCIEBit 0: EN0
BitSzer.PoleDostępOpis
01EN`rw`channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software.
11TCIE`rw`transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
21HTIE`rw`half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
31TEIE`rw`transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
41DIR`rw`data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
51CIRC`rw`circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
61PINC`rw`peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
71MINC`rw`memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
8–92PSIZE`rw`peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR=1 and the memory source if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR=1 and the peripheral source if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
10–112MSIZE`rw`memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR=1 and the memory destination if DIR=0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR=1 and the peripheral destination if DIR=0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
12–132PL`rw`priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
141MEM2MEM`rw`memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
Rejestr: NDTR7:  0x40020084

DMA channel x number of data register

Bit 31: zarezerwowany31Bit 30: zarezerwowanyBit 29: zarezerwowanyBit 28: zarezerwowany28Bit 27: zarezerwowanyBit 26: zarezerwowanyBit 25: zarezerwowanyBit 24: zarezerwowany24Bit 23: zarezerwowanyBit 22: zarezerwowanyBit 21: zarezerwowanyBit 20: zarezerwowany20Bit 19: zarezerwowanyBit 18: zarezerwowanyBit 17: zarezerwowanyBit 16: zarezerwowany16Bit 15: NDTBit 14: NDTBit 13: NDTBit 12: NDT12Bit 11: NDTBit 10: NDTBit 9: NDTBit 8: NDT8Bit 7: NDTBit 6: NDTBit 5: NDTBit 4: NDT4Bit 3: NDTBit 2: NDTBit 1: NDTBit 0: NDT0
BitSzer.PoleDostępOpis
0–1516NDT`rw`number of data to transfer (0 to 216-1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC=0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC=1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN=1).
Rejestr: PAR7:  0x40020088

DMA channel x peripheral address register

Bit 31: PA31Bit 30: PABit 29: PABit 28: PA28Bit 27: PABit 26: PABit 25: PABit 24: PA24Bit 23: PABit 22: PABit 21: PABit 20: PA20Bit 19: PABit 18: PABit 17: PABit 16: PA16Bit 15: PABit 14: PABit 13: PABit 12: PA12Bit 11: PABit 10: PABit 9: PABit 8: PA8Bit 7: PABit 6: PABit 5: PABit 4: PA4Bit 3: PABit 2: PABit 1: PABit 0: PA0
BitSzer.PoleDostępOpis
0–3132PA`rw`peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0]=01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE=10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR=1 and the memory source address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR=1 and the peripheral source address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).
Rejestr: MAR7:  0x4002008C

DMA channel x memory address register

Bit 31: MA31Bit 30: MABit 29: MABit 28: MA28Bit 27: MABit 26: MABit 25: MABit 24: MA24Bit 23: MABit 22: MABit 21: MABit 20: MA20Bit 19: MABit 18: MABit 17: MABit 16: MA16Bit 15: MABit 14: MABit 13: MABit 12: MA12Bit 11: MABit 10: MABit 9: MABit 8: MA8Bit 7: MABit 6: MABit 5: MABit 4: MA4Bit 3: MABit 2: MABit 1: MABit 0: MA0
BitSzer.PoleDostępOpis
0–3132MA`rw`peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0]=01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE=10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR=1 and the memory destination address if DIR=0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR=1 and the peripheral destination address if DIR=0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN=1).