GPIO
GPIOA 0x50000000
11 rejestrów/klastrów w tym peryferium.
Rejestr: MODER 0x50000000
rw
GPIO port mode register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0–1 | 2 | MODER0: | — | Port x configuration pin 0 |
| 2–3 | 2 | MODER1: | — | Port x configuration pin 1 |
| 4–5 | 2 | MODER2: | — | Port x configuration pin 2 |
| 6–7 | 2 | MODER3: | — | Port x configuration pin 3 |
| 8–9 | 2 | MODER4: | — | Port x configuration pin 4 |
| 10–11 | 2 | MODER5: | — | Port x configuration pin 5 |
| 12–13 | 2 | MODER6: | — | Port x configuration pin 6 |
| 14–15 | 2 | MODER7: | — | Port x configuration pin 7 |
| 16–17 | 2 | MODER8: | — | Port x configuration pin 8 |
| 18–19 | 2 | MODER9: | — | Port x configuration pin 9 |
| 20–21 | 2 | MODER10: | — | Port x configuration pin 10 |
| 22–23 | 2 | MODER11: | — | Port x configuration pin 11 |
| 24–25 | 2 | MODER12: | — | Port x configuration pin 12 |
| 26–27 | 2 | MODER13: | — | Port x configuration pin 13 |
| 28–29 | 2 | MODER14: | — | Port x configuration pin 14 |
| 30–31 | 2 | MODER15: | — | Port x configuration pin 15 |
Rejestr: OTYPER 0x50000004
rw
GPIO port output type register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0 | 1 | OT0: | — | Port x configuration pin 0 |
| 1 | 1 | OT1: | — | Port x configuration pin 1 |
| 2 | 1 | OT2: | — | Port x configuration pin 2 |
| 3 | 1 | OT3: | — | Port x configuration pin 3 |
| 4 | 1 | OT4: | — | Port x configuration pin 4 |
| 5 | 1 | OT5: | — | Port x configuration pin 5 |
| 6 | 1 | OT6: | — | Port x configuration pin 6 |
| 7 | 1 | OT7: | — | Port x configuration pin 7 |
| 8 | 1 | OT8: | — | Port x configuration pin 8 |
| 9 | 1 | OT9: | — | Port x configuration pin 9 |
| 10 | 1 | OT10: | — | Port x configuration pin 10 |
| 11 | 1 | OT11: | — | Port x configuration pin 11 |
| 12 | 1 | OT12: | — | Port x configuration pin 12 |
| 13 | 1 | OT13: | — | Port x configuration pin 13 |
| 14 | 1 | OT14: | — | Port x configuration pin 14 |
| 15 | 1 | OT15: | — | Port x configuration pin 15 |
Rejestr: OSPEEDR 0x50000008
rw
GPIO port output speed register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0–1 | 2 | OSPEEDR0: | — | Port x configuration pin 0 |
| 2–3 | 2 | OSPEEDR1: | — | Port x configuration pin 1 |
| 4–5 | 2 | OSPEEDR2: | — | Port x configuration pin 2 |
| 6–7 | 2 | OSPEEDR3: | — | Port x configuration pin 3 |
| 8–9 | 2 | OSPEEDR4: | — | Port x configuration pin 4 |
| 10–11 | 2 | OSPEEDR5: | — | Port x configuration pin 5 |
| 12–13 | 2 | OSPEEDR6: | — | Port x configuration pin 6 |
| 14–15 | 2 | OSPEEDR7: | — | Port x configuration pin 7 |
| 16–17 | 2 | OSPEEDR8: | — | Port x configuration pin 8 |
| 18–19 | 2 | OSPEEDR9: | — | Port x configuration pin 9 |
| 20–21 | 2 | OSPEEDR10: | — | Port x configuration pin 10 |
| 22–23 | 2 | OSPEEDR11: | — | Port x configuration pin 11 |
| 24–25 | 2 | OSPEEDR12: | — | Port x configuration pin 12 |
| 26–27 | 2 | OSPEEDR13: | — | Port x configuration pin 13 |
| 28–29 | 2 | OSPEEDR14: | — | Port x configuration pin 14 |
| 30–31 | 2 | OSPEEDR15: | — | Port x configuration pin 15 |
Rejestr: PUPDR 0x5000000C
rw
GPIO port pull-up/pull-down register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0–1 | 2 | PUPDR0: | — | Port x configuration pin 0 |
| 2–3 | 2 | PUPDR1: | — | Port x configuration pin 1 |
| 4–5 | 2 | PUPDR2: | — | Port x configuration pin 2 |
| 6–7 | 2 | PUPDR3: | — | Port x configuration pin 3 |
| 8–9 | 2 | PUPDR4: | — | Port x configuration pin 4 |
| 10–11 | 2 | PUPDR5: | — | Port x configuration pin 5 |
| 12–13 | 2 | PUPDR6: | — | Port x configuration pin 6 |
| 14–15 | 2 | PUPDR7: | — | Port x configuration pin 7 |
| 16–17 | 2 | PUPDR8: | — | Port x configuration pin 8 |
| 18–19 | 2 | PUPDR9: | — | Port x configuration pin 9 |
| 20–21 | 2 | PUPDR10: | — | Port x configuration pin 10 |
| 22–23 | 2 | PUPDR11: | — | Port x configuration pin 11 |
| 24–25 | 2 | PUPDR12: | — | Port x configuration pin 12 |
| 26–27 | 2 | PUPDR13: | — | Port x configuration pin 13 |
| 28–29 | 2 | PUPDR14: | — | Port x configuration pin 14 |
| 30–31 | 2 | PUPDR15: | — | Port x configuration pin 15 |
Rejestr: IDR 0x50000010
ro
GPIO port input data register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0 | 1 | IDR0: | — | Port input data pin 0 |
| 1 | 1 | IDR1: | — | Port input data pin 1 |
| 2 | 1 | IDR2: | — | Port input data pin 2 |
| 3 | 1 | IDR3: | — | Port input data pin 3 |
| 4 | 1 | IDR4: | — | Port input data pin 4 |
| 5 | 1 | IDR5: | — | Port input data pin 5 |
| 6 | 1 | IDR6: | — | Port input data pin 6 |
| 7 | 1 | IDR7: | — | Port input data pin 7 |
| 8 | 1 | IDR8: | — | Port input data pin 8 |
| 9 | 1 | IDR9: | — | Port input data pin 9 |
| 10 | 1 | IDR10: | — | Port input data pin 10 |
| 11 | 1 | IDR11: | — | Port input data pin 11 |
| 12 | 1 | IDR12: | — | Port input data pin 12 |
| 13 | 1 | IDR13: | — | Port input data pin 13 |
| 14 | 1 | IDR14: | — | Port input data pin 14 |
| 15 | 1 | IDR15: | — | Port input data pin 15 |
Rejestr: ODR 0x50000014
rw
GPIO port output data register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0 | 1 | ODR0: | — | Port output data pin 0 |
| 1 | 1 | ODR1: | — | Port output data pin 1 |
| 2 | 1 | ODR2: | — | Port output data pin 2 |
| 3 | 1 | ODR3: | — | Port output data pin 3 |
| 4 | 1 | ODR4: | — | Port output data pin 4 |
| 5 | 1 | ODR5: | — | Port output data pin 5 |
| 6 | 1 | ODR6: | — | Port output data pin 6 |
| 7 | 1 | ODR7: | — | Port output data pin 7 |
| 8 | 1 | ODR8: | — | Port output data pin 8 |
| 9 | 1 | ODR9: | — | Port output data pin 9 |
| 10 | 1 | ODR10: | — | Port output data pin 10 |
| 11 | 1 | ODR11: | — | Port output data pin 11 |
| 12 | 1 | ODR12: | — | Port output data pin 12 |
| 13 | 1 | ODR13: | — | Port output data pin 13 |
| 14 | 1 | ODR14: | — | Port output data pin 14 |
| 15 | 1 | ODR15: | — | Port output data pin 15 |
Rejestr: BSRR 0x50000018
wo
GPIO port bit set/reset register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0 | 1 | BS0: | — | Port x set pin 0 |
| 1 | 1 | BS1: | — | Port x set pin 1 |
| 2 | 1 | BS2: | — | Port x set pin 2 |
| 3 | 1 | BS3: | — | Port x set pin 3 |
| 4 | 1 | BS4: | — | Port x set pin 4 |
| 5 | 1 | BS5: | — | Port x set pin 5 |
| 6 | 1 | BS6: | — | Port x set pin 6 |
| 7 | 1 | BS7: | — | Port x set pin 7 |
| 8 | 1 | BS8: | — | Port x set pin 8 |
| 9 | 1 | BS9: | — | Port x set pin 9 |
| 10 | 1 | BS10: | — | Port x set pin 10 |
| 11 | 1 | BS11: | — | Port x set pin 11 |
| 12 | 1 | BS12: | — | Port x set pin 12 |
| 13 | 1 | BS13: | — | Port x set pin 13 |
| 14 | 1 | BS14: | — | Port x set pin 14 |
| 15 | 1 | BS15: | — | Port x set pin 15 |
| 16 | 1 | BR0: | — | Port x reset pin 0 |
| 17 | 1 | BR1: | — | Port x reset pin 1 |
| 18 | 1 | BR2: | — | Port x reset pin 2 |
| 19 | 1 | BR3: | — | Port x reset pin 3 |
| 20 | 1 | BR4: | — | Port x reset pin 4 |
| 21 | 1 | BR5: | — | Port x reset pin 5 |
| 22 | 1 | BR6: | — | Port x reset pin 6 |
| 23 | 1 | BR7: | — | Port x reset pin 7 |
| 24 | 1 | BR8: | — | Port x reset pin 8 |
| 25 | 1 | BR9: | — | Port x reset pin 9 |
| 26 | 1 | BR10: | — | Port x reset pin 10 |
| 27 | 1 | BR11: | — | Port x reset pin 11 |
| 28 | 1 | BR12: | — | Port x reset pin 12 |
| 29 | 1 | BR13: | — | Port x reset pin 13 |
| 30 | 1 | BR14: | — | Port x reset pin 14 |
| 31 | 1 | BR15: | — | Port x reset pin 15 |
Rejestr: LCKR 0x5000001C
rw
GPIO port configuration lock register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0 | 1 | LCK0: | — | Port x lock pin 0 |
| 1 | 1 | LCK1: | — | Port x lock pin 1 |
| 2 | 1 | LCK2: | — | Port x lock pin 2 |
| 3 | 1 | LCK3: | — | Port x lock pin 3 |
| 4 | 1 | LCK4: | — | Port x lock pin 4 |
| 5 | 1 | LCK5: | — | Port x lock pin 5 |
| 6 | 1 | LCK6: | — | Port x lock pin 6 |
| 7 | 1 | LCK7: | — | Port x lock pin 7 |
| 8 | 1 | LCK8: | — | Port x lock pin 8 |
| 9 | 1 | LCK9: | — | Port x lock pin 9 |
| 10 | 1 | LCK10: | — | Port x lock pin 10 |
| 11 | 1 | LCK11: | — | Port x lock pin 11 |
| 12 | 1 | LCK12: | — | Port x lock pin 12 |
| 13 | 1 | LCK13: | — | Port x lock pin 13 |
| 14 | 1 | LCK14: | — | Port x lock pin 14 |
| 15 | 1 | LCK15: | — | Port x lock pin 15 |
| 16 | 1 | LCKK: | — | Port x lock bit y (y= 0..15) |
Rejestr: AFRL 0x50000020
rw
GPIO alternate function low register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0–3 | 4 | AFREL0: | — | Alternate function selection for port x bit y (y = 0..7) |
| 4–7 | 4 | AFREL1: | — | Alternate function selection for port x bit y (y = 0..7) |
| 8–11 | 4 | AFREL2: | — | Alternate function selection for port x bit y (y = 0..7) |
| 12–15 | 4 | AFREL3: | — | Alternate function selection for port x bit y (y = 0..7) |
| 16–19 | 4 | AFREL4: | — | Alternate function selection for port x bit y (y = 0..7) |
| 20–23 | 4 | AFREL5: | — | Alternate function selection for port x bit y (y = 0..7) |
| 24–27 | 4 | AFREL6: | — | Alternate function selection for port x bit y (y = 0..7) |
| 28–31 | 4 | AFREL7: | — | Alternate function selection for port x bit y (y = 0..7) |
Rejestr: AFRH 0x50000024
rw
GPIO alternate function high register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0–3 | 4 | AFREL8 | — | Alternate function selection for port x bit y (y = 8..15) |
| 4–7 | 4 | AFREL9 | — | Alternate function selection for port x bit y (y = 8..15) |
| 8–11 | 4 | AFREL10 | — | Alternate function selection for port x bit y (y = 8..15) |
| 12–15 | 4 | AFREL11 | — | Alternate function selection for port x bit y (y = 8..15) |
| 16–19 | 4 | AFREL12 | — | Alternate function selection for port x bit y (y = 8..15) |
| 20–23 | 4 | AFREL13 | — | Alternate function selection for port x bit y (y = 8..15) |
| 24–27 | 4 | AFREL14 | — | Alternate function selection for port x bit y (y = 8..15) |
| 28–31 | 4 | AFREL15 | — | Alternate function selection for port x bit y (y = 8..15) |
Rejestr: BRR 0x50000028
wo
port bit reset register
| Bit | Szer. | Pole | Dostęp | Opis |
|---|---|---|---|---|
| 0 | 1 | BR0: | — | Port x reset pin 0 |
| 1 | 1 | BR1: | — | Port x reset pin 1 |
| 2 | 1 | BR2: | — | Port x reset pin 2 |
| 3 | 1 | BR3: | — | Port x reset pin 3 |
| 4 | 1 | BR4: | — | Port x reset pin 4 |
| 5 | 1 | BR5: | — | Port x reset pin 5 |
| 6 | 1 | BR6: | — | Port x reset pin 6 |
| 7 | 1 | BR7: | — | Port x reset pin 7 |
| 8 | 1 | BR8: | — | Port x reset pin 8 |
| 9 | 1 | BR9: | — | Port x reset pin 9 |
| 10 | 1 | BR10: | — | Port x reset pin 10 |
| 11 | 1 | BR11: | — | Port x reset pin 11 |
| 12 | 1 | BR12: | — | Port x reset pin 12 |
| 13 | 1 | BR13: | — | Port x reset pin 13 |
| 14 | 1 | BR14: | — | Port x reset pin 14 |
| 15 | 1 | BR15: | — | Port x reset pin 15 |