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I2C1 0x40005400

11 rejestrów/klastrów w tym peryferium.

Rejestr: CR1 0x40005400

Control register 1

Bit	Szer.	Pole	Dostęp	Opis
0	1	PE	`rw`	Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.
1	1	TXIE	`rw`	TX Interrupt enable
2	1	RXIE	`rw`	RX Interrupt enable
3	1	ADDRIE	`rw`	Address match Interrupt enable (slave only)
4	1	NACKIE	`rw`	Not acknowledge received Interrupt enable
5	1	STOPIE	`rw`	Stop detection Interrupt enable
6	1	TCIE	`rw`	Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)
7	1	ERRIE	`rw`	Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)
8–11	4	DNF	`rw`	Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0).
12	1	ANFOFF	`rw`	Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0).
14	1	TXDMAEN	`rw`	DMA transmission requests enable
15	1	RXDMAEN	`rw`	DMA reception requests enable
16	1	SBC	`rw`	Slave byte control This bit is used to enable hardware byte control in slave mode.
17	1	NOSTRETCH	`rw`	Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0).
18	1	WUPEN	`rw`	Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to . Note: WUPEN can be set only when DNF = '0000'
19	1	GCEN	`rw`	General call enable
20	1	SMBHEN	`rw`	SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to .
21	1	SMBDEN	`rw`	SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to .
22	1	ALERTEN	`rw`	SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to .
23	1	PECEN	`rw`	PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to .

Rejestr: CR2 0x40005404

Control register 2

Bit	Szer.	Pole	Dostęp	Opis
0–9	10	SADD	`rw`	Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed.
10	1	RD_WRN	`rw`	Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed.
11	1	ADD10	`rw`	10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed.
12	1	HEAD10R	`rw`	10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed.
13	1	START	`rw`	Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1' to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0' to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set.
14	1	STOP	`rw`	Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing '0' to this bit has no effect.
15	1	NACK	`rw`	NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing '0' to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value.
16–23	8	NBYTES	`rw`	Number of bytes The number of bytes to be transmitted/received is programmed there. This field is don't care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed.
24	1	RELOAD	`rw`	NBYTES reload mode This bit is set and cleared by software.
25	1	AUTOEND	`rw`	Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set.
26	1	PECBYTE	`rw`	Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing '0' to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'. Refer to .

Rejestr: OAR1 0x40005408

Own address register 1

Bit	Szer.	Pole	Dostęp	Opis
0–9	10	OA1	`rw`	Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN=0.
10	1	OA1MODE	`rw`	Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0.
15	1	OA1EN	`rw`	Own Address 1 enable

Rejestr: OAR2 0x4000540C

Own address register 2

Bit	Szer.	Pole	Dostęp	Opis
1–7	7	OA2	`rw`	Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN=0.
8–10	3	OA2MSK	`rw`	Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches.
15	1	OA2EN	`rw`	Own Address 2 enable

Rejestr: TIMINGR 0x40005410

Timing register

Bit	Szer.	Pole	Dostęp	Opis
0–7	8	SCLL:	—	SCL low period (master mode)
8–15	8	SCLH:	—	SCL high period (master mode)
16–19	4	SDADEL:	—	Data hold time
20–23	4	SCLDEL:	—	Data setup time
28–31	4	PRESC:	—	Timing prescaler

Rejestr: TIMEOUTR 0x40005414

Status register 1

Bit	Szer.	Pole	Dostęp	Opis
0–11	12	TIMEOUTA	`rw`	Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0.
12	1	TIDLE	`rw`	Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0.
15	1	TIMOUTEN	`rw`	Clock timeout enable
16–27	12	TIMEOUTB	`rw`	Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0.
31	1	TEXTEN	`rw`	Extended clock timeout enable

Rejestr: ISR: 0x40005418

Interrupt and Status register

Bit	Szer.	Pole	Dostęp	Opis
0	1	TXE	`rw`	Transmit data register empty (transmitters)
1	1	TXIS	`rw`	Transmit interrupt status (transmitters)
2	1	RXNE	`ro`	Receive data register not empty (receivers)
3	1	ADDR	`ro`	Address matched (slave mode)
4	1	NACKF	`ro`	Not acknowledge received flag
5	1	STOPF	`ro`	Stop detection flag
6	1	TC	`ro`	Transfer Complete (master mode)
7	1	TCR	`ro`	Transfer Complete Reload
8	1	BERR	`ro`	Bus error
9	1	ARLO	`ro`	Arbitration lost
10	1	OVR	`ro`	Overrun/Underrun (slave mode)
11	1	PECERR	`ro`	PEC Error in reception
12	1	TIMEOUT	`ro`	Timeout or t_low detection flag
13	1	ALERT	`ro`	SMBus alert
15	1	BUSY	`ro`	Bus busy
16	1	DIR	`ro`	Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1).
17–23	7	ADDCODE	`ro`	Address match code (Slave mode)

Rejestr: ICR 0x4000541C

Interrupt clear register

Bit	Szer.	Pole	Dostęp	Opis
3	1	ADDRCF:	—	Address Matched flag clear
4	1	NACKCF:	—	Not Acknowledge flag clear
5	1	STOPCF:	—	Stop detection flag clear
8	1	BERRCF:	—	Bus error flag clear
9	1	ARLOCF:	—	Arbitration lost flag clear
10	1	OVRCF:	—	Overrun/Underrun flag clear
11	1	PECCF:	—	PEC Error flag clear
12	1	TIMOUTCF:	—	Timeout detection flag clear
13	1	ALERTCF:	—	Alert flag clear

Rejestr: PECR 0x40005420

PEC register

Bit	Szer.	Pole	Dostęp	Opis
0–7	8	PEC:	—	Packet error checking register

Rejestr: RXDR 0x40005424

Receive data register

Bit	Szer.	Pole	Dostęp	Opis
0–7	8	RXDATA:	—	8-bit receive data

Rejestr: TXDR 0x40005428

Transmit data register

Bit	Szer.	Pole	Dostęp	Opis
0–7	8	TXDATA:	—	8-bit transmit data