RTC / Watchdog

TAMP 0x4000B000

12 rejestrów/klastrów w tym peryferium.

Rejestr: CR1: 0x4000B000

TAMP control register 1

Bit	Szer.	Pole	Dostęp	Opis
0	1	TAMP1E	`rw`	Tamper detection on TAMP_IN1 enable
1	1	TAMP2E	`rw`	Tamper detection on TAMP_IN2 enable
2	1	TAMP3E	`rw`	Tamper detection on TAMP_IN3 enable
18	1	ITAMP3E	`rw`	Internal tamper 3 enable: LSE monitoring
19	1	ITAMP4E	`rw`	Internal tamper 4 enable: HSE monitoring
20	1	ITAMP5E	`rw`	Internal tamper 5 enable: RTC calendar overflow
21	1	ITAMP6E	`rw`	Internal tamper 6 enable: ST manufacturer readout

Rejestr: CR2: 0x4000B004

TAMP control register 2

Bit	Szer.	Pole	Dostęp	Opis
0	1	TAMP1NOER	`rw`	Tamper 1 no erase
1	1	TAMP2NOER	`rw`	Tamper 2 no erase
2	1	TAMP3NOER	`rw`	Tamper 3 no erase
16	1	TAMP1MSK	`rw`	Tamper 1 mask The tamper 1 interrupt must not be enabled when TAMP1MSK is set.
17	1	TAMP2MSK	`rw`	Tamper 2 mask The tamper 2 interrupt must not be enabled when TAMP2MSK is set.
18	1	TAMP3MSK	`rw`	Tamper 3 mask The tamper 3 interrupt must not be enabled when TAMP3MSK is set.
24	1	TAMP1TRG	`rw`	Active level for tamper 1 input (active mode disabled) If TAMPFLT = 00 Tamper 1 input rising edge and high level triggers a tamper detection event. If TAMPFLT = 00 Tamper 1 input falling edge and low level triggers a tamper detection event.
25	1	TAMP2TRG	`rw`	Active level for tamper 2 input (active mode disabled) If TAMPFLT = 00 Tamper 2 input rising edge and high level triggers a tamper detection event. If TAMPFLT = 00 Tamper 2 input falling edge and low level triggers a tamper detection event.
26	1	TAMP3TRG	`rw`	Active level for tamper 3 input (active mode disabled) If TAMPFLT = 00 Tamper 3 input rising edge and high level triggers a tamper detection event. If TAMPFLT = 00 Tamper 3 input falling edge and low level triggers a tamper detection event.

Rejestr: FLTCR: 0x4000B00C

TAMP filter control register

Bit	Szer.	Pole	Dostęp	Opis
0–2	3	TAMPFREQ	`rw`	Tamper sampling frequency Determines the frequency at which each of the TAMP_INx inputs are sampled.
3–4	2	TAMPFLT	`rw`	TAMP_INx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the TAMP_INx inputs.
5–6	2	TAMPPRCH	`rw`	TAMP_INx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the TAMP_INx inputs.
7	1	TAMPPUDIS	`rw`	TAMP_INx pull-up disable This bit determines if each of the TAMPx pins are precharged before each sample.

Rejestr: IER: 0x4000B02C

TAMP interrupt enable register

Bit	Szer.	Pole	Dostęp	Opis
0	1	TAMP1IE	`rw`	Tamper 1 interrupt enable
1	1	TAMP2IE	`rw`	Tamper 2 interrupt enable
2	1	TAMP3IE	`rw`	Tamper 3 interrupt enable
18	1	ITAMP3IE	`rw`	Internal tamper 3 interrupt enable: LSE monitoring
19	1	ITAMP4IE	`rw`	Internal tamper 4 interrupt enable: HSE monitoring
20	1	ITAMP5IE	`rw`	Internal tamper 5 interrupt enable: RTC calendar overflow
21	1	ITAMP6IE	`rw`	Internal tamper 6 interrupt enable: ST manufacturer readout

Rejestr: SR: 0x4000B030

TAMP status register

Bit	Szer.	Pole	Dostęp	Opis
0	1	TAMP1F	`ro`	TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP1 input.
1	1	TAMP2F	`ro`	TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP2 input.
2	1	TAMP3F	`ro`	TAMP3 detection flag This flag is set by hardware when a tamper detection event is detected on the TAMP3 input.
18	1	ITAMP3F	`ro`	LSE monitoring tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 3.
19	1	ITAMP4F	`ro`	HSE monitoring tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 4.
20	1	ITAMP5F	`ro`	RTC calendar overflow tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 5.
21	1	ITAMP6F	`ro`	ST manufacturer readout tamper detection flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 6.

Rejestr: MISR: 0x4000B034

TAMP masked interrupt status register

Bit	Szer.	Pole	Dostęp	Opis
0	1	TAMP1MF	`ro`	TAMP1 interrupt masked flag This flag is set by hardware when the tamper 1 interrupt is raised.
1	1	TAMP2MF	`ro`	TAMP2 interrupt masked flag This flag is set by hardware when the tamper 2 interrupt is raised.
2	1	TAMP3MF	`ro`	TAMP3 interrupt masked flag This flag is set by hardware when the tamper 3 interrupt is raised.
18	1	ITAMP3MF	`ro`	LSE monitoring tamper interrupt masked flag This flag is set by hardware when the internal tamper 3 interrupt is raised.
19	1	ITAMP4MF	`ro`	HSE monitoring tamper interrupt masked flag This flag is set by hardware when the internal tamper 4 interrupt is raised.
20	1	ITAMP5MF	`ro`	RTC calendar overflow tamper interrupt masked flag This flag is set by hardware when the internal tamper 5 interrupt is raised.
21	1	ITAMP6MF	`ro`	ST manufacturer readout tamper interrupt masked flag This flag is set by hardware when the internal tamper 6 interrupt is raised.

Rejestr: SCR: 0x4000B03C

TAMP status clear register

Bit	Szer.	Pole	Dostęp	Opis
0	1	CTAMP1F	`wo`	Clear TAMP1 detection flag Writing 1 in this bit clears the TAMP1F bit in the TAMP_SR register.
1	1	CTAMP2F	`wo`	Clear TAMP2 detection flag Writing 1 in this bit clears the TAMP2F bit in the TAMP_SR register.
2	1	CTAMP3F	`wo`	Clear TAMP3 detection flag Writing 1 in this bit clears the TAMP3F bit in the TAMP_SR register.
18	1	CITAMP3F	`wo`	Clear ITAMP3 detection flag Writing 1 in this bit clears the ITAMP3F bit in the TAMP_SR register.
19	1	CITAMP4F	`wo`	Clear ITAMP4 detection flag Writing 1 in this bit clears the ITAMP4F bit in the TAMP_SR register.
20	1	CITAMP5F	`wo`	Clear ITAMP5 detection flag Writing 1 in this bit clears the ITAMP5F bit in the TAMP_SR register.
21	1	CITAMP6F	`wo`	Clear ITAMP6 detection flag Writing 1 in this bit clears the ITAMP6F bit in the TAMP_SR register.

Rejestr: BKP0R: 0x4000B100

TAMP backup 0 register

Bit	Szer.	Pole	Dostęp	Opis
0–31	32	BKP	`rw`	The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled.

Rejestr: BKP1R: 0x4000B104

TAMP backup 1 register

Bit	Szer.	Pole	Dostęp	Opis
0–31	32	BKP	`rw`	The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled.

Rejestr: BKP2R: 0x4000B108

TAMP backup 2 register

Bit	Szer.	Pole	Dostęp	Opis
0–31	32	BKP	`rw`	The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled.

Rejestr: BKP3R: 0x4000B10C

TAMP backup 3 register

Bit	Szer.	Pole	Dostęp	Opis
0–31	32	BKP	`rw`	The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled.

Rejestr: BKP4R: 0x4000B110

TAMP backup 4 register

Bit	Szer.	Pole	Dostęp	Opis
0–31	32	BKP	`rw`	The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled.