Counter enable Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs.
1
1
UDIS
`rw`
Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
2
1
URS
`rw`
Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
3
1
OPM
`rw`
One-pulse mode
7
1
ARPE
`rw`
Auto-reload preload enable
11
1
UIFREMAP
`rw`
UIF status bit remapping
Rejestr: CR20x40001004
rw
control register 2
Bit
Szer.
Pole
Dostęp
Opis
4–6
3
MMS
`rw`
Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
Rejestr: DIER0x4000100C
rw
DMA/Interrupt enable register
Bit
Szer.
Pole
Dostęp
Opis
0
1
UIE
`rw`
Update interrupt enable
8
1
UDE
`rw`
Update DMA request enable
Rejestr: SR0x40001010
rw
status register
Bit
Szer.
Pole
Dostęp
Opis
0
1
UIF
`rw`
Update interrupt flag
Rejestr: EGR0x40001014
wo
event generation register
Bit
Szer.
Pole
Dostęp
Opis
0
1
UG
`wo`
Update generation This bit can be set by software, it is automatically cleared by hardware.
Rejestr: CNT0x40001024
rw
counter
Brak zdefiniowanych pól bitowych.
Rejestr: CNT160x40001024
rw
16-bit counter register
Bit
Szer.
Pole
Dostęp
Opis
0–15
16
CNT
`rw`
Counter value
0–15
16
CNT
`rw`
counter value
31
1
UIFCPY
`ro`
UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0.